28nm Planar Middle-of-Line Integration: Process Flow Principles and Strain Engineering Mechanisms

Role in the Complete Flow

The middle-of-line (MOL) module in a 28nm planar logic flow sits at a critical juncture between front-end-of-line (FEOL) transistor formation and back-end-of-line (BEOL) interconnect construction [P4]. It receives from upstream a fully formed gate stack — including high-k dielectric, metal gate, and poly-Si dummy gate in a gate-last integration scheme — along with completed source/drain (S/D) implant regions and sidewall spacers [P1]. The S/D areas have already undergone amorphization through ion implantation, creating the structural precondition that the MOL module will exploit for stress memorization [P2]. The shallow trench isolation (STI) topology has been planarized and defined, establishing the active-to-isolation boundaries that constrain subsequent film deposition and etch profiles [P3].

What the MOL module must deliver downstream is twofold: a transistor channel that carries a stable, memorized tensile strain to boost electron mobility in NMOS devices, and a clean, planar surface topography suitable for silicidation and subsequent contact formation [P2]. The SMT oxide deposition and associated buffer oxide layers serve as temporary mechanical stressors during a thermal anneal cycle; after the stress is transferred and frozen into the silicon lattice, these layers are removed so that downstream contact and interconnect modules can proceed without obstruction [P1][A1]. The MOL module also must not disturb the threshold voltage tuning already established during gate stack formation, nor introduce layout proximity effects (LPEs) that would cause unacceptable device-to-device performance variation [P1].

In the broader context of the 28nm Planar process flow, the MOL module is the last opportunity to engineer channel strain through dislocation-based mechanisms before the process moves into the contact and metallization regime [P4]. It is also the last thermal treatment step that interacts directly with the S/D junctions and the gate stack before silicide formation, making its thermal budget a critical constraint on junction integrity and dopant profile stability [T2].

Entry State and Sequence Logic

Upstream Dependencies

The 28nm MOL module begins after spacer formation and S/D implantation are complete [P1]. At this entry point, the poly-Si dummy gate has been patterned and the S/D regions have been amorphized by implant damage [P1]. The integration logic demands that the MOL sequence not begin until spacers are fully formed, because the spacer defines the lateral boundary that the SMT stressor cap layer will mechanically couple to during the subsequent anneal [P1]. If spacer formation is incomplete or non-uniform, the stress transfer from the cap layer to the channel will be spatially inconsistent, producing unacceptable drive-current variation across the die [P2].

The 28nm Planar sidewall spacer integration process flow directly determines the geometric envelope within which the MOL module operates [P4]. The spacer width controls how much of the S/D region is exposed to the SMT cap layer, and the spacer material's mechanical properties determine how efficiently stress is transmitted laterally toward the channel [P2].

Downstream Deliverables

After the MOL module completes — stressor cap deposition, thermal anneal, cap removal, and surface preparation — the process hands off to contact formation and silicidation [T1]. The S/D regions must be clean and free of residual stressor material so that nickel silicide can form uniformly [T1]. Any residual SMT oxide or buffer oxide on the S/D active area will block silicidation and create contact resistance failures [A1]. The gate top surface must also be exposed for later gate replacement (in gate-last flows) or cap removal, depending on the specific integration variant [A1].

The sequence logic is strictly ordered: SMT cap deposition → high-temperature anneal → cap and buffer oxide removal → surface clean → silicide formation → 28nm Planar contact formation process flow [P3]. Reordering any of these steps would break either the stress memorization mechanism or the silicide quality [P1][P2].

Physical and Chemical Mechanisms

Stress Memorization: Dislocation Formation and Channel Strain

The core physical mechanism of the SMT module is the creation and retention of crystallographic defects — specifically edge dislocations and stacking faults — in the S/D regions, which generate a longitudinal tensile strain field that extends into the channel [P1]. During the thermal anneal step, the amorphized S/D silicon undergoes solid-phase epitaxial regrowth (SPER) [P2]. As the amorphous-to-crystalline transition proceeds, the recrystallization front encounters lattice distortion from the implant damage and from the mechanical constraint imposed by the overlying stressor cap layer [P1]. This constraint suppresses lateral volume expansion during recrystallization, and the resulting lattice mismatch nucleates dislocations at the S/D-to-channel interface [P1][A1].

These dislocations persist after the anneal because they are thermodynamically stabilized by the local stress field and by the lattice mismatch between the heavily doped recrystallized S/D and the channel silicon [P1]. The tensile strain they introduce into the channel modifies the silicon band structure, reducing the electron effective mass and enhancing electron mobility in NMOS devices [T2]. The strain-field coupling follows solid-mechanics principles: the stressor cap layer applies a mechanical boundary condition during recrystallization, and the poly-Si gate's own volume change during amorphization-recrystallization contributes additional stress transfer [P2].

Stressor Cap Layer: Stress Shift as the Key Variable

A critical insight from strain-engineering research is that the effectiveness of SMT is governed not by the absolute magnitude of the stressor cap's intrinsic stress — whether tensile or compressive — but by the stress shift that occurs between deposition and the post-anneal state [P2]. A compressive silicon nitride (SiN) cap layer can transition toward tensile stress during rapid thermal annealing (RTA), producing a larger stress change than a conventionally tensile SiN layer [P2]. This larger stress shift more effectively constrains the lateral expansion of the poly-Si gate during recrystallization, injecting a stronger effective tensile strain into the channel [P2].

The poly-Si gate plays a dual role: it acts as a mechanical coupling medium that transfers stress from the cap to the channel, and its own amorphization-recrystallization volume change contributes to the net stress state [P2]. The degree of amorphization in the poly-Si — controlled by pre-amorphization implant (PAI) conditions — directly influences the volume expansion during recrystallization and thus the stress-transfer efficiency [P2]. A more deeply amorphized poly-Si layer undergoes more extensive recrystallization, generating greater volume swelling and a stronger stress-memorization effect [P2].

SMT Oxide Deposition Integration Principles

The SMT oxide deposition step involves depositing a buffer oxide layer beneath the SiN stressor cap layer [P1]. The buffer oxide serves as a mechanical decoupling and adhesion layer: it prevents direct contact between the high-stress SiN and the underlying silicon or spacer materials, reducing the risk of delamination or cracking during the thermal cycle [A1]. The buffer oxide also conformally covers the gate and S/D topography, creating a uniform surface for SiN deposition and ensuring that the stressor cap's mechanical boundary condition is applied evenly across the device [P2].

The integration logic of the buffer oxide is that it must be thick enough to provide mechanical decoupling and step coverage, yet thin enough that it does not dilute the stress transfer from the SiN cap to the poly-Si gate and S/D regions [P2]. This tradeoff is fundamental to the SMT oxide deposition integration principles: a thicker buffer improves adhesion and crack resistance but weakens stress coupling; a thinner buffer strengthens stress transfer but risks cap delamination and non-uniform coverage [A1][P2].

Oxygen Diffusion and Layout Proximity Effects

A secondary but increasingly significant mechanism during the high-temperature SMT anneal is oxygen diffusion from the STI oxide into the high-k dielectric layer along the gate-to-STI overlap region [P1]. At elevated temperatures, oxygen in the STI becomes mobile and can diffuse laterally into the HfO₂-based high-k dielectric, altering the interfacial chemical state and shifting the effective work function of the metal gate [P1]. This causes the threshold voltage to become sensitive to layout parameters such as channel width and the spacing between active areas (DSTS-X and DSTS-Y) [P1].

This mechanism means that the SMT anneal does not only affect strain — it also introduces a thermal-budget-driven chemical modification of the gate stack [P1]. The layout proximity effects arise because devices with different STI spacing experience different oxygen diffusion paths and durations, leading to device-to-device threshold variation that is directly attributable to the SMT thermal cycle [P1]. At the 28nm node, these effects are non-negligible and must be accounted for in the MOL module design [P4].

Interfaces and Failure Propagation

MOL-to-FEOL Interface: Junction Integrity

The MOL module's thermal budget directly interacts with the S/D junctions formed during FEOL [T1]. The high-temperature SMT anneal can cause dopant redistribution in the S/D regions, potentially broadening the junction and increasing junction leakage [T2]. If the anneal temperature is too high or the duration too long, the dopant profile established during implantation and spike anneal can be erased, degrading short-channel control and increasing off-state leakage [P1]. The direction of this tradeoff is clear: stronger SMT (higher thermal budget) yields better drive current through enhanced strain, but at the cost of junction integrity and leakage control [P1][T2].

MOL-to-Gate-Stack Interface: Work Function Stability

As discussed above, oxygen diffusion during the SMT anneal can alter the high-k/metal-gate interface chemistry, shifting the effective work function and introducing threshold voltage variation [P1]. This is a directional tradeoff: the anneal temperature that maximizes dislocation formation and stress memorization also maximizes oxygen diffusion and work-function drift [P1]. The integration engineer must balance these competing effects, and the choice of anneal strategy — whether conventional high-temperature SMT or a modified low-temperature SPER-assisted approach — determines which direction the tradeoff leans [P1].

MOL-to-Contact Interface: Surface Cleanliness

After the SMT cap and buffer oxide are removed, the S/D and gate surfaces must be residue-free for silicide formation [P1]. Any residual SMT oxide or nitride on the active S/D area will block nickel silicide nucleation, creating high contact resistance and device failure [A1]. The removal process — typically a combination of dry and wet etching — must be selective enough to remove the cap and buffer completely without consuming the underlying silicon or damaging the spacers [P3]. Incomplete removal propagates forward as contact yield loss; over-removal propagates as junction damage and increased leakage [A1].

Layout Proximity Effect Propagation

The LPEs introduced during the SMT anneal — width effect, DSTS-X, and DSTS-Y — propagate downstream as measurable device performance variation in the wafer acceptance test (WAT) [P1]. Devices with narrow channel widths or close STI spacing exhibit different threshold voltages and drive currents than wide, isolated devices, even though they were designed identically [T2]. This variation is not a defect in the conventional sense but a systematic process-induced pattern that must be modeled and compensated in circuit design [T1]. If left unmitigated, it can cause timing margin failures in logic paths that mix devices of different layout configurations [P1].

Walk the Real Module

To see how these principles translate into an actual 28nm planar process sequence, you can explore the interactive MOL module flow step by step [P4]. The sequence begins with SMT oxide deposition, proceeds through stressor cap deposition and the critical thermal anneal, and culminates in cap removal and surface preparation for downstream contact formation [P1].

Open MOL Step 127 in the interactive flow

In the interactive flow, you can trace how each step's entry state depends on the prior step's exit state, and how the SMT oxide deposition integration principles discussed above map to specific process operations [P1]. The flow also illustrates the sequence dependencies: the buffer oxide must precede the SiN stressor cap, the anneal must follow cap deposition, and the removal must complete before silicidation begins — none of these steps can be reordered without breaking the stress memorization chain [P1][P2][A1].

Related Learning Paths

For engineers seeking to build a complete picture of 28nm planar integration, the MOL module is best studied in conjunction with its nearest neighbors:

• The 28nm Planar sidewall spacer integration process flow defines the geometric and mechanical boundary conditions that the MOL stressor cap relies upon [P4]. Understanding spacer formation is essential for understanding why stress transfer efficiency depends on spacer width and material stiffness [P3].

• The 28nm Planar contact formation process flow is the immediate downstream consumer of the MOL module's output [P4]. The surface condition, residue levels, and topography left by MOL cap removal directly determine contact resistance and silicide quality [P3].

• The 28nm Planar process flow overview provides the full module-level context, showing how MOL fits between FEOL transistor formation and BEOL interconnect construction in the complete integration scheme [P4].

Future Outlook

As planar CMOS scaling pushed toward and past the 28nm node, the SMT module faced increasing pressure from layout proximity effects and thermal budget constraints [P1]. The modified low-temperature SPER-assisted SMT approach — which generates edge dislocations at lower temperatures before a subsequent high-temperature activation spike — represents a direction that preserves stress gains while reducing oxygen diffusion and LPE severity [P1]. This approach decouples dislocation formation from the high thermal budget that drives unwanted diffusion, and it points toward a general strategy for advanced planar nodes: separating the strain-engineering thermal cycle from the activation thermal cycle [A1].

Beyond planar devices, the principles of dislocation-based strain engineering have been extended to FinFET structures, where oriented dislocation planes can be introduced beneath STI and S/D regions to modulate channel stress in three dimensions [A1]. The transition from planar to FinFET geometry changes the stress transfer mechanics — the three-dimensional confinement of the fin makes strain modulation more sensitive and effective, but also more difficult to control uniformly [A1]. For future gate-all-around (GAA) and nanosheet devices, the challenge will be even greater, as the fully surrounded channel geometry limits the available surfaces through which external stressors can couple to the channel [T2].

The MOL module's role as the last direct channel-strain-engineering opportunity in the flow means that its evolution will continue to track the broader industry trend toward lower thermal budgets, more precise defect engineering, and tighter layout-dependent variation control [P2]. The principles established at 28nm — stress shift as the key variable, buffer oxide as mechanical decoupler, oxygen diffusion as a secondary chemical risk — remain conceptually relevant even as device geometries change [P1][P2].