28nm Planar Sidewall Spacer Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow

The sidewall spacer module sits at a critical junction in the 28nm Planar process flow, bridging gate stack formation and source/drain engineering [P2]. By the time this module begins, the gate electrode and gate dielectric have already been patterned and the lightly doped drain (LDD) implant has been introduced into the substrate adjacent to the gate edges [P3]. The SPACER module process flow must then create dielectric sidewalls along the vertical flanks of the gate stack, which serve as self-aligned masks for the subsequent heavily doped source/drain implant [P3]. In the 28nm Planar node, multiple spacer pairs may be employed — sometimes several pairs bracket the gate stack — to satisfy competing requirements of implant offset, silicidation isolation, and contact alignment [A1].

What this module delivers downstream is twofold (Engineering Practice). First, it physically defines the lateral offset between the lightly doped region near the channel and the heavily doped source/drain region, thereby controlling the electric field profile at the drain junction and suppressing hot-carrier injection (HCI) [P3]. Second, it electrically isolates the gate stack from the source/drain regions during subsequent silicidation, preventing catastrophic shorting between the gate, source, and drain [P1]. Without properly formed sidewall spacers, the self-aligned implant strategy that underpins the entire 28nm Planar source-drain integration process flow would collapse, and device reliability would degrade sharply [P3].

The spacer also influences parasitic capacitances and overlap capacitances that directly affect switching speed and power dissipation [A2]. Because the spacer material sits in close proximity to the channel region, its dielectric constant, width, and profile all contribute to the device's transconductance and threshold behavior [P3]. Understanding the 28nm Planar process flow in its entirety requires appreciating how the spacer module serves as both a physical barrier and an electrical shaping element [T2].

Entry State and Sequence Logic

Upstream Dependencies

When the SPACER module begins, the wafer has completed gate patterning, gate dielectric formation, and the first (LDD) ion implantation step [T2]. The gate stack at this point consists of the gate dielectric, the polysilicon or replacement-metal gate electrode, and possibly a hard mask layer — typically silicon oxide (SiO2) or silicon nitride (SiN) — that was used during gate patterning [P1]. The gate sidewall profile must be substantially vertical because any taper or bowing directly propagates into spacer dimensional variation [P3]. The LDD implant has already created a lightly doped region extending from the gate edge, and this region's lateral extent will be finalized by the spacer width minus subsequent lateral diffusion of the heavily doped junction [P3].

The entry state is therefore sensitive to upstream gate etch quality [P3]. If the gate etch left polymer residues, sidewall roughness, or profile deviations, the conformal deposition that follows will amplify these imperfections into non-uniform spacer widths [P2]. In the 28nm sidewall spacer integration, the gate stack height-to-spacer-film-thickness aspect ratio must be maintained above a minimum threshold to ensure that the anisotropic etchback produces spacers of predictable width rather than consuming the spacer material entirely [P3].

Downstream Deliverables

After spacer formation, the next modules include the heavily doped source/drain implant, activation anneal, and silicidation [P3]. The spacer must survive these subsequent thermal and chemical processes without dimensional drift or material degradation [P4]. If SiO2 is used as the spacer material, its etch selectivity to silicon during subsequent cleaning steps must be sufficient to preserve spacer integrity [T1]. If silicon nitride is used, it can additionally serve as an etch-stop layer for self-aligned contact formation in later back-end-of-line (BEOL) steps [P1]. The choice of spacer material and the number of spacer pairs thus ripple forward into the 28nm Planar middle-of-line integration process flow, affecting contact alignment margins and parasitic resistance [P2].

Physical and Chemical Mechanisms

Conformal Deposition

The spacer formation mechanism begins with conformal deposition of a dielectric film — most commonly SiO2 or silicon nitride — over the entire wafer surface, including the vertical sidewalls of the gate stack [P2]. The conformality of this deposition is governed by the transport and surface reaction kinetics of the precursor species [P1]. In chemical vapor deposition (CVD), gas-phase precursors such as silane and oxygen, or dichlorosilane and nitrous oxide, react at the substrate surface to form solid SiO2 [T1]. The ratio of surface reaction rate to gas-phase diffusion rate determines step coverage: when surface reactions are relatively slow compared to precursor transport, the film deposits uniformly even on vertical sidewalls, producing the high conformality required for spacer applications [P2].

In the 28nm Planar SPACER module process flow, atomic layer deposition (ALD) may also be employed for Spacer2 Oxide Deposition, where the integration principles demand even tighter conformality and thickness control than conventional CVD can provide [P4]. ALD relies on self-limiting surface reactions where precursor pulses alternate with purge cycles, ensuring layer-by-layer growth that is inherently conformal regardless of substrate topology (Engineering Practice). The Spacer2 oxide deposition step is particularly important when a dual-spacer scheme is used: the first spacer (often nitride) provides the primary implant mask, while Spacer2 (often oxide) refines the spacer profile and provides additional isolation for silicidation [P4].

Anisotropic Etchback

After conformal deposition, a blanket anisotropic etchback removes the horizontal film on planar surfaces while preserving the material on vertical sidewalls [P2]. This is the defining step of spacer formation (Engineering Practice). The anisotropy arises from directional ion bombardment in a plasma environment: energetic ions accelerated through the plasma sheath strike the wafer surface predominantly along the surface normal, enhancing the etch rate of horizontal films relative to vertical sidewall films [P1]. The chemical component of the etch — involving radical species adsorbing and reacting with the surface to form volatile products — operates isotropically but is overwhelmed by the directional ion enhancement on horizontal surfaces [P1].

For SiO2 spacer etching, fluorocarbon-based plasma chemistries are commonly employed [P4]. The etch mechanism involves a dynamic balance between chemical etching and polymer passivation: fluorine radicals react with SiO2 to form volatile silicon fluorides, while carbon-fluorine species deposit polymer layers that passivate silicon surfaces [P4]. Ion bombardment clears the polymer from oxide surfaces, allowing etching to proceed, but the ion energy is insufficient to fully clear the passivation on silicon, yielding high oxide-to-silicon selectivity [P4]. The ratio of radical generation rate to directional ion energy is critical: excessive radical generation drives polymerization to the point of etch stall, while insufficient ion energy fails to clear passivation and also stalls the etch [P4].

The width of the resulting spacer is determined primarily by the deposited film thickness, with corrections for etch bias and the conformality factor — the ratio of sidewall film thickness to planar film thickness [P3]. The effective LDD region length can be expressed qualitatively as the physical spacer length adjusted by the lateral diffusion of the lightly doped and heavily doped junctions: L_{n^-} = l_{n^-} + D - l_{n^+}, where D is the physical spacer length, l_{n^-} and l_{n^+} are the lateral diffusion lengths of the respective junctions [P3].

Self-Alignment Logic

The self-alignment principle is what makes the spacer architecture so powerful (Engineering Practice). Rather than using lithography to define the offset between the LDD and the heavily d drain — which would introduce overlay error — the spacer width is determined entirely by deposition thickness and etch control, both of which can be controlled with far better uniformity than lithographic overlay [P2]. This principle was recognized early in the development of LDD field-effect transistors (LDDFETs), where oxide sidewall spacers formed by reactive ion etching (RIE) enabled excellent control and repeatability of the lightly doped region length without requiring additional lithography masks [P3].

Interfaces and Failure Propagation

Spacer–Gate Sidewall Interface

The interface between the spacer and the gate sidewall is the most critical boundary in this module [P3]. Any gate sidewall roughness, taper, or residue from the gate etch step propagates directly into spacer width variation, which in turn modulates the LDD region length and the electric field distribution at the drain junction [P3]. A narrower-than-designed spacer reduces the LDD offset, increasing peak electric fields and exacerbating hot-carrier degradation; a wider-than-designed spacer increases parasitic resistance in the source/drain access path, degrading drive current [P3].

Spacer–Substrate Interface

During the anisotropic etchback, the etch must terminate cleanly on the substrate silicon without causing excessive silicon loss [P4]. Over-etching extends beyond the endpoint to ensure complete removal of horizontal oxide, but excessive over-etch consumes silicon from the source/drain regions, creating junction damage and potentially increasing contact resistance [P3]. The selectivity of the etch chemistry to silicon is therefore a paramount concern [P4]. Fluorocarbon chemistries that build passivating polymer layers on silicon surfaces can achieve high selectivity, but the process window is narrow and highly sensitive to the plasma energy balance [P4].

Spacer–Silicidation Interface

After spacer formation and source/drain implantation, the silicidation module must form low-resistance silicide on the exposed source, drain, and gate surfaces [P4]. The spacer must prevent silicide formation on the gate sidewall, which would short the gate to the source/drain [P1]. If the spacer is too thin or has pinholes, nickel or cobalt from the silicidation process can penetrate to the gate sidewall, creating a resistive or shorting path [P3]. This failure mode is especially dangerous because it may not be detected until late electrical testing, when transistor leakage or threshold voltage shifts reveal the problem (Engineering Practice).

Multi-Spacer Tradeoffs

In advanced 28nm Planar integration, multiple spacer pairs introduce additional tradeoffs [A2]. Each additional spacer pair increases the total dielectric volume surrounding the gate, which raises overlap capacitance and can degrade switching performance [P3]. However, additional spacers also provide larger silicidation isolation margins and better implant masking redundancy [A1]. The integration engineer must balance these competing effects, selecting the minimum number of spacer pairs that satisfy reliability requirements without excessively penalizing AC performance (Engineering Practice).

Failure Propagation Summary

The directional tradeoffs can be summarized as follows: thicker deposition improves spacer robustness but increases parasitic capacitance; higher etch selectivity protects silicon but narrows the process window; more spacer pairs improve isolation but degrade speed [P3]. Each decision propagates downstream — from spacer dimensions to LDD length, from LDD length to electric field, from electric field to hot-carrier lifetime, and from parasitic capacitance to circuit delay [P3].

Walk the Real Module

To see how these principles are operationalized in the actual 28nm Planar process flow, the interactive module provides a step-by-step view of the SPACER sequence [T2]. The module begins with the gate stack already in place and walks through the conformal deposition, anisotropic etchback, and inspection steps that define the final spacer profile [P2]. You can Open SPACER Step 104 in the interactive flow to examine the specific sequence operations and their ordering (Engineering Practice).

In the interactive flow, the SPACER module illustrates how the deposition step creates a conformal SiO2 film over the gate top, sidewalls, and exposed substrate, followed by the etchback step that selectively removes horizontal material [P4]. The endpoint detection — typically based on optical emission — signals when the horizontal film has been cleared, and a controlled over-etch ensures complete removal while minimizing substrate damage [P1]. The flow also shows how the Spacer2 oxide deposition step fits within the broader sequence, where it may serve as a second-layer spacer that refines the profile established by the first spacer layer [P4].

Understanding this module in context requires connecting it to the 28nm Planar source-drain integration process flow, where the heavily doped implant and subsequent activation anneal depend critically on the spacer dimensions established here [P3]. The spacer width directly determines how far the heavy implant is displaced from the channel, and any variation in spacer width translates into variation in the effective channel length and the series resistance of the source/drain extension regions [P3].

Related Learning Paths

For engineers seeking to deepen their understanding of the 28nm Planar platform, several adjacent topics merit exploration:

• Gate stack formation: The gate etch profile that precedes spacer deposition determines the quality of the spacer itself [T2]. Studying the gate module reveals how sidewall verticality and roughness constraints propagate into the SPACER module [P3].

• Source/drain engineering: The spacer's downstream impact is most visible in the source/drain module, where implant alignment, junction depth, and silicidation all depend on spacer geometry [P3]. The 28nm Planar source-drain integration process flow article covers these dependencies in detail [T2].

• Middle-of-line integration: The spacer material and dimensions influence contact formation and parasitic elements in the middle-of-line stack [P3]. The 28nm Planar middle-of-line integration process flow article explains how spacer choices propagate into contact alignment and resistive-capacitive (RC) delay [P2].

• Self-aligned patterning techniques: The spacer-as-mask concept extends beyond transistor fabrication into pitch multiplication for lithography, where sidewall spacer quadruple patterning (SAQP) uses the same deposition–etch principle to achieve sub-lithographic dimensions [P2].

Future Outlook

As semiconductor technology continues to scale beyond the 28nm Planar node, the sidewall spacer module evolves in several directions [T2]. In fin field-effect transistor (FinFET) and gate-all-around (GAA) architectures, the spacer must conform to three-dimensional fin or nanosheet surfaces, placing even greater demands on deposition conformality and etch uniformity [P3]. The self-alignment principle remains unchanged, but the geometric complexity increases dramatically (Engineering Practice).

Advanced spacer materials are also under investigation (Engineering Practice). Silicon nitride doped with carbon, silicon oxynitride, and other engineered dielectrics offer tunable dielectric constants and improved etch selectivity [A1]. These materials aim to reduce parasitic capacitance while maintaining the isolation and masking functions that spacers must provide [P4].

ALD continues to gain prominence for spacer deposition due to its inherent conformality and atomic-scale thickness control [P3]. As device dimensions shrink, the ability to deposit spacer films with atomic-level precision becomes essential, and the integration principles of Spacer2 oxide deposition established at the 28nm node provide the foundation for these advanced applications [T2].

Finally, the broader trend toward spacer-based self-aligned patterning — as demonstrated in SAQP for NAND flash memory [P2] — suggests that the deposition–etch spacer mechanism will remain a workhorse of semiconductor manufacturing for years to come, whether applied to transistor spacers or to pitch multiplication masks.