28nm Planar Sidewall Spacer Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow

The sidewall spacer module sits at a critical junction in the 28nm Planar process flow, bridging gate stack formation and source/drain engineering. By the time this module begins, the gate electrode and gate dielectric have already been patterned and the lightly doped drain (LDD) implant has been introduced into the substrate adjacent to the gate edges. The SPACER module process flow must then create dielectric sidewalls along the vertical flanks of the gate stack, which serve as self-aligned masks for the subsequent heavily doped source/drain implant. In the 28nm Planar node, multiple spacer pairs may be employed to satisfy competing requirements of implant offset, silicidation isolation, and contact alignment.

What this module delivers downstream is twofold. First, it physically defines the lateral offset between the lightly doped region near the channel and the heavily doped source/drain region, thereby controlling the electric field profile at the drain junction and suppressing hot-carrier injection (HCI). Second, it electrically isolates the gate stack from the source/drain regions during subsequent silicidation, preventing shorting between the gate, source, and drain. Without properly formed sidewall spacers, the self-aligned implant strategy that underpins the entire 28nm Planar source-drain integration process flow would fail, and device reliability would degrade sharply.

The spacer also influences parasitic capacitances and overlap capacitances that directly affect switching speed and power dissipation. Because the spacer material sits in close proximity to the channel region, its dielectric constant, width, and profile all contribute to the device's transconductance and threshold behavior. Understanding the 28nm Planar process flow in its entirety requires appreciating how the spacer module serves as both a physical barrier and an electrical shaping element.

Entry State and Sequence Logic

Upstream Dependencies

When the SPACER module begins, the wafer has completed gate patterning, gate dielectric formation, and the first LDD ion implantation step. The gate stack at this point consists of the gate dielectric, the gate electrode (polysilicon or dummy gate for replacement metal gate flows), and a hard mask layer—typically silicon oxide (SiO2) or silicon nitride (SiN)—used during gate patterning. The gate sidewall profile must be substantially vertical because any taper or bowing directly propagates into spacer dimensional variation. The LDD implant has already created a lightly doped region extending from the gate edge, and this region's lateral extent will be finalized by the spacer width minus subsequent lateral diffusion of the heavily doped junction.

The entry state is therefore sensitive to upstream gate etch quality. If the gate etch left polymer residues, sidewall roughness, or profile deviations, the conformal deposition that follows will amplify these imperfections into non-uniform spacer widths. In the 28nm sidewall spacer integration, the gate stack height-to-spacer-film-thickness aspect ratio must be maintained above a design threshold to ensure that the anisotropic etchback produces spacers of predictable width rather than consuming the spacer material entirely.

Downstream Deliverables

After spacer formation, the next modules include the heavily doped source/drain implant, activation anneal, and silicidation. The spacer must survive these subsequent thermal and chemical processes without dimensional drift or material degradation. If SiO2 is used as the spacer material, its etch selectivity to silicon during subsequent cleaning steps must be sufficient to preserve spacer integrity. If silicon nitride is used, it can additionally serve as an etch-stop layer for self-aligned contact formation in later back-end-of-line (BEOL) steps. The choice of spacer material and the number of spacer pairs thus ripple forward into the 28nm Planar middle-of-line integration process flow, affecting contact alignment margins and parasitic resistance.

Physical and Chemical Mechanisms

Conformal Deposition

The spacer formation mechanism begins with conformal deposition of a dielectric film—most commonly SiO2 or silicon nitride—over the entire wafer surface, including the vertical sidewalls of the gate stack. Dielectric film deposition for spacers requires a lower thermal budget compared to thermal oxidation, helping limit the thermal exposure of existing junctions [T1]. The conformality of this deposition is governed by the transport and surface reaction kinetics of the precursor species. In chemical vapor deposition (CVD), gas-phase precursors react at the substrate surface to form solid dielectric layers. The ratio of surface reaction rate to gas-phase diffusion rate determines step coverage: when surface reactions are relatively slow compared to precursor transport, the film deposits uniformly even on vertical sidewalls, producing the high conformality required for spacer applications.

In the 28nm Planar SPACER module process flow, atomic layer deposition (ALD) is also employed for Spacer2 oxide deposition, where integration demands tight conformality and precise thickness control. The layer-by-layer self-limited growth mechanism of ALD enables uniform thin films to be deposited with high conformality across dense topology . The Spacer2 oxide deposition step is particularly important when a dual-spacer scheme is used: the first spacer (often nitride) provides the primary implant mask, while Spacer2 (often oxide) refines the spacer profile and provides additional isolation for silicidation.

Anisotropic Etchback

After conformal deposition, a blanket anisotropic etchback removes the horizontal film on planar surfaces while preserving the material on vertical sidewalls. The anisotropy arises from directional ion bombardment in a plasma environment: energetic ions accelerated through the plasma sheath strike the wafer surface predominantly along the surface normal, enhancing the etch rate of horizontal films relative to vertical sidewall films. The chemical component of the etch—involving radical species adsorbing and reacting with the surface to form volatile products—operates isotropically but is overwhelmed by directional ion enhancement on horizontal surfaces.

For SiO2 spacer etching, fluorocarbon-based plasma chemistries are commonly employed. The etch mechanism involves a balance between chemical etching and polymer passivation: fluorine radicals react with SiO2 to form volatile silicon fluorides, while carbon-fluorine species deposit polymer layers that passivate silicon surfaces. Ion bombardment clears the polymer from oxide surfaces, allowing etching to proceed, while passivating films protect the silicon substrate to maintain selectivity. The ratio of radical generation rate to directional ion energy is critical: excessive radical generation drives polymerization to the point of etch stall, while insufficient ion energy fails to clear passivation.

The width of the resulting spacer is determined primarily by the deposited film thickness, with corrections for etch bias and the conformality factor—the ratio of sidewall film thickness to planar film thickness. The effective LDD region length can be expressed qualitatively as the physical spacer length adjusted by the lateral diffusion of the lightly doped and heavily doped junctions: L_{n^-} = l_{n^-} + D - l_{n^+}, where D is the physical spacer length, and l_{n^-} and l_{n^+} are the lateral diffusion lengths of the respective junctions.

Self-Alignment Logic

The self-alignment principle eliminates reliance on lithography to define the offset between the LDD and the heavily doped source/drain region. Rather than using an optical mask—which would introduce overlay error—the spacer width is determined by deposition thickness and anisotropic etch control, achieving tighter dimensional control than lithographic overlay tolerances. This principle ensures that source/drain junction offsets are intrinsically locked to the patterned gate edges across the entire wafer.

Interfaces and Failure Propagation

Spacer–Gate Sidewall Interface

The interface between the spacer and the gate sidewall is a critical boundary in this module. Any gate sidewall roughness, taper, or residue from the gate etch step propagates directly into spacer width variation, which in turn modulates the LDD region length and the electric field distribution at the drain junction. A narrower-than-designed spacer reduces the LDD offset, increasing peak electric fields and exacerbating hot-carrier degradation; a wider-than-designed spacer increases parasitic series resistance in the source/drain access path, degrading drive current.

Spacer–Substrate Interface

During anisotropic etchback, the etch must terminate cleanly on the substrate silicon without causing excessive silicon loss or severe lattice damage. Over-etching extends beyond the nominal endpoint to ensure complete removal of horizontal dielectric material, but excessive over-etch consumes silicon from the active regions, creating junction defects and potentially increasing contact resistance. Fluorocarbon chemistries that build passivating polymer layers on silicon surfaces achieve high selectivity, though the process window remains sensitive to plasma energy balance.

Spacer–Silicidation Interface

After spacer formation and source/drain implantation, the silicidation module forms low-resistance silicide on exposed source, drain, and gate surfaces. The spacer must prevent silicide formation on the gate sidewall to avoid shorting the gate to the source/drain. If the spacer is too thin or contains pinholes, nickel or cobalt from the silicidation process can migrate along the gate sidewall, creating leakage paths or direct short circuits.

Multi-Spacer Tradeoffs

In advanced 28nm Planar integration, multiple spacer pairs introduce additional tradeoffs. Each additional spacer pair increases the dielectric volume surrounding the gate, which raises overlap capacitance and can penalize switching speed. However, additional spacers provide larger silicidation isolation margins and better implant masking flexibility. Process engineering must balance these competing factors to satisfy reliability targets without compromising high-frequency performance.

Failure Propagation Summary

The integration tradeoffs can be summarized directly: thicker deposition improves spacer masking and isolation robustness but increases parasitic capacitance; higher etch selectivity protects the silicon surface but narrows the plasma process window; additional spacer pairs improve isolation redundancy but increase gate overlap capacitance. Each choice propagates downstream—from spacer dimensions to LDD length, electric field profiles, hot-carrier lifetime, and circuit switching delay.

Walk the Real Module

To see how these principles are operationalized in the actual 28nm Planar process flow, the interactive sequence details the SPACER process module. The sequence begins with the gate stack already in place and walks through conformal deposition, anisotropic etchback, and wet clean operations that define the final spacer profile. You can Open SPACER Step 104 in the interactive flow to examine the specific sequence operations and their ordering.

In the interactive flow, the SPACER module illustrates how the Spacer2 Oxide Deposition step creates a conformal SiO2 film over the gate top, sidewalls, and exposed substrate, followed by nitride deposition and anisotropic etchback that selectively removes horizontal material. Controlled over-etch ensures complete removal while protecting the active silicon surface.

Understanding this module in context requires connecting it to the 28nm Planar source-drain integration process flow, where the heavily doped implant and subsequent activation anneal depend on the spacer dimensions established here. The spacer width directly dictates how far the heavy implant is displaced from the channel, directly impacting the effective channel length and series resistance.

Related Learning Paths

For engineers seeking to deepen their understanding of the 28nm Planar platform, several adjacent topics merit exploration:

• Gate stack formation: The gate etch profile that precedes spacer deposition determines the quality of the spacer itself. Studying the gate module reveals how sidewall verticality and roughness constraints propagate into the SPACER module.
• Source/drain engineering: The spacer's downstream impact is most visible in the source/drain module, where implant alignment, junction depth, and silicidation all depend on spacer geometry. The 28nm Planar source-drain integration process flow article covers these dependencies in detail.
• Middle-of-line integration: The spacer material and dimensions influence contact formation and parasitic elements in the middle-of-line stack. The 28nm Planar middle-of-line integration process flow article explains how spacer choices propagate into contact alignment and resistive-capacitive (RC) delay.
• Self-aligned patterning techniques: The spacer-as-mask concept extends beyond transistor fabrication into pitch multiplication for lithography, where sidewall spacer patterning uses similar deposition–etch principles to achieve sub-lithographic dimensions.

Future Outlook

As technology scales beyond planar architectures, the sidewall spacer module continues to evolve. In FinFET and gate-all-around (GAA) architectures, spacers must conformally wrap around three-dimensional fin or nanosheet structures, placing stringent requirements on deposition conformality and etch directional control while maintaining the fundamental self-alignment principle.

Advanced dielectric materials continue to be integrated. Carbon-doped silicon nitride, silicon oxynitride, and low-k dielectric spacers offer reduced dielectric constants to lower parasitic overlap capacitance while preserving etch selectivity and thermal stability during downstream annealing.

Finally, atomic layer processes are increasingly indispensable for spacer fabrication. Precise thickness control at the single-nanometer scale ensures that spacer-defined junction offsets remain consistent across complex layouts, confirming that deposition–etch spacer integration remains a core building block of advanced semiconductor manufacturing.