28nm Planar Source-Drain Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow

The source-drain (SD) module in the 28nm planar logic flow sits at a pivotal position within the front-end-of-line (FEOL) sequence [P2]. It receives a structure that has already undergone well/channel implantation, extension (also called lightly doped drain or LDD) implantation, and first spacer formation — all steps that define the channel doping profile and the initial gate-edge architecture [T1]. The SD module's responsibility is to complete the transistor's terminal regions: forming the deep source/drain junctions, introducing the appropriate stressors for mobility enhancement, and preparing the surface for silicidation and subsequent contact formation [T1].

In the 28nm planar node specifically, this module must deliver several critical outcomes downstream [P1]. First, it must create electrically active, sufficiently shallow junctions that maintain acceptable short-channel behavior — the junction depth and lateral diffusion directly influence drain-induced barrier lowering (DIBL) and subthreshold swing [T2]. Second, for pFET devices, it must embed silicon-germanium (SiGe) in the source/drain regions to induce compressive strain in the channel, boosting hole mobility [P1]. Third, it must leave the poly gate intact and protected throughout a series of etch, epitaxy, and deposition steps, so that the gate stack — whether gate-first or replacement-gate — remains undamaged for downstream processing [P3]. Finally, the module must produce a surface topography compatible with subsequent nickel (or nickel-platinum) silicidation, contact etch, and metal-one (M1) dual-damascene processing [T3].

The SD module thus serves as the bridge between channel engineering and interconnect formation (Engineering Practice). Everything upstream — 28nm Planar well and channel implant integration process flow — establishes the electrostatic framework, while everything downstream depends on the junction quality, strain state, and surface integrity that this module delivers [P1]. The 28nm Planar process flow as a whole is only as robust as the SD module's ability to balance junction scaling, stress engineering, and gate protection simultaneously [P1].

Entry State and Sequence Logic

When the SD module begins, the wafer carries a partially completed transistor: the gate stack (including high-k dielectric, metal gate electrode, and polysilicon gate) has been patterned; extension implants have been introduced under the first spacer; and the first spacer itself has been deposited and etched to define the LDD offset [T1]. The isolation structures — shallow trench isolation (STI) — are already in place, and the channel regions have received their well and channel-stop implants (Engineering Practice). The entry surface is thus a patterned landscape of gate lines sitting above active silicon regions, with spacers hugging the gate sidewalls [A2].

The sequence logic of the 28nm SD module follows a carefully ordered chain of operations (Engineering Practice). After first spacer formation, the module typically proceeds through:

1 (Engineering Practice). SiGe hardmask deposition — A silicon nitride (SiN) hardmask is deposited over the wafer to serve as a selective etch and epitaxy template, particularly for pFET source/drain cavity formation [T3]. 2. Source/drain implantation — High-dose implants (arsenic for nFET, boron species for pFET) are introduced to form the deep junctions [T1]. 3. SiGe epitaxial growth (pFET) — For pFET devices, the original silicon in the source/drain areas is recessed and replaced with embedded SiGe (eSiGe) to act as a stressor [P1]. 4. Anneal/activation — A high-temperature thermal treatment activates the implanted dopants and repairs lattice damage while minimizing diffusion to preserve shallow junctions [T3]. 5. Silicide formation — A metal layer (typically nickel-based) is deposited and reacted with exposed silicon to form low-resistance silicide contacts [T2].

The integration dependencies are stringent (Engineering Practice). The SiN hardmask deposition must occur before the SiGe epitaxy because the hardmask defines the boundaries within which the eSiGe grows — without it, the epitaxial material would not be confined to the source/drain regions [A1]. Poly gate protection is essential throughout: any exposure of the polysilicon gate to the SiGe etch or epitaxy chemistry could degrade the gate stack, alter the threshold voltage, or introduce parasitic conduction paths [P3]. The SiGe hardmask thus serves a dual purpose — it templates the epitaxy region and it shields the gate from process damage [A2].

The relationship between the SD module and the preceding 28nm Planar sidewall spacer integration process flow is also critical [T3]. The spacer dimensions determine the source/drain-to-gate offset, which in turn governs the overlap capacitance and the extension resistance [P2]. If the spacer is too narrow, the SD implant will encroach too close to the channel, worsening short-channel effects; if too wide, the series resistance increases and the strain transfer from eSiGe to the channel becomes less efficient [P1].

Physical and Chemical Mechanisms

Strain Engineering via Embedded SiGe

The central physical mechanism in the 28nm pFET SD module is strain transfer from embedded SiGe to the silicon channel [P1]. SiGe has a larger lattice constant than pure silicon due to the larger atomic radius of germanium [P3]. When SiGe is grown epitaxially in the source/drain recesses adjacent to the channel, the lattice mismatch generates a compressive strain field that propagates into the channel region [P1].

This compressive strain modifies the valence-band structure of the silicon channel [P1]. Specifically, it lifts the degeneracy between the heavy-hole and light-hole bands, reducing the effective mass of holes along the channel direction [P1]. Lower effective mass means higher carrier mobility, which translates directly into higher drive current (Ion) for the same gate overdrive [T2]. The strain also reduces inter-valence-band scattering, further enhancing mobility [P1].

The efficiency of strain transfer depends strongly on the morphology of the eSiGe [P1]. Research has shown that when the eSiGe forms specific crystallographic facets — particularly (111) planes — near the channel interface, and when the angle between the eSiGe facet and the channel is increased, the longitudinal compressive strain (Sxx) coupling becomes more efficient [P1]. This is because the strain field geometry is dictated by the shape of the SiGe-Si interface, and certain facet orientations channel the strain more directly along the transport direction [P1].

The epitaxial growth process itself involves selective deposition: silicon and germanium precursors are introduced in a chemical vapor deposition (CVD) environment, and growth occurs only on exposed silicon surfaces (not on oxide or nitride) [T3]. The selectivity is achieved through a combination of surface chemistry — the precursor adsorption and decomposition kinetics differ between silicon and dielectric surfaces — and the presence of chlorine-containing etchant species that remove any nucleation on non-silicon surfaces [T1].

Doping and Junction Formation

For the deep source/drain junctions, ion implantation is the primary doping method [T3]. The physics of ion implantation involves high-energy ions penetrating the silicon lattice, coming to rest at a characteristic depth determined by the implant energy and the stopping power of the material [T3]. The resulting dopant distribution follows an approximately Gaussian profile, with the peak concentration at a projected range below the surface [T1].

The subsequent thermal treatment serves two purposes: activating the dopants (moving them substitutionally into the lattice sites where they act as donors or acceptors) and repairing the implantation-induced lattice damage [T1]. The challenge is that thermal treatment also causes diffusion — dopants redistribute — which deepens the junction [T3]. At the 28nm node, maintaining shallow junctions while achieving full activation requires careful thermal budget management, typically using rapid thermal annealing (RTA) or spike anneals that deliver high peak temperatures for very short durations [T3].

The Si/SiGe lattice mismatch also plays a role in junction formation for pFETs [P3]. The bandgap of SiGe is narrower than that of silicon, with the valence band edge shifted upward [P3]. This bandgap engineering effect, combined with the compressive strain, means that the eSiGe source/drain regions not only provide stress but also modify the band alignment at the source-channel interface, potentially reducing the source-side barrier and improving carrier injection [P3].

Silicidation Chemistry

Silicide formation at the source/drain and gate surfaces involves a solid-state reaction between a deposited metal (nickel or nickel-platinum alloy) and silicon [T1]. At elevated temperature, the metal reacts with silicon to form a metal silicide phase — a compound with metallic conductivity that serves as the contact interface [T2]. The reaction consumes silicon from the substrate, creating a slightly recessed silicide-silicon interface [T3].

The silicidation is self-aligned because the metal only reacts where it is in direct contact with exposed silicon [T1]. The spacer regions, covered by dielectric, do not react, preventing short circuits between the gate and source/drain (Engineering Practice). The selectivity of the silicide formation thus depends on the integrity of the spacer and hardmask layers that isolate the gate from the source/drain regions [T1].

Interfaces and Failure Propagation

The SD module interfaces with multiple upstream and downstream modules, and failures here propagate in characteristic directions (Engineering Practice).

Upstream interface — spacer and extension: If the first spacer is compromised (e (Engineering Practice).g., insufficient thickness or poor sidewall coverage), the SD implant will diffuse too close to the channel during activation anneal, causing junction encroachment [T3]. This manifests as increased overlap capacitance, worsened DIBL, and potentially threshold voltage shifts [T1]. The extension resistance also increases if the spacer is too wide, because the current path from the channel to the deep source/drain must traverse a longer lightly-doped region [T2].

Gate stack interface: The poly gate protection function of the SiN hardmask is critical [P3]. If the hardmask fails — through pinholes, cracking, or inadequate thickness — the SiGe etch chemistry can attack the polysilicon gate [P3]. This leads to gate height loss, work function alteration, or even gate shorting to the source/drain through silicide bridging [P3]. The consequences are catastrophic: threshold voltage variation, increased gate leakage, and potential yield loss [P3].

SiGe-channel interface: The quality of the eSiGe epitaxy directly affects strain transfer efficiency [P1]. If the SiGe growth conditions produce rough surfaces, threading dislocations, or faceting that deviates from the optimal (111) orientation, the compressive strain in the channel will be reduced [P1]. Dislocations in the SiGe can also propagate into the channel, acting as recombination centers that degrade carrier lifetime and increase junction leakage [A1].

Downstream interface — silicide and contact: The surface topography left by the SD module determines the silicide formation quality [T1]. If the eSiGe surface is rough or if residual hardmask material remains, the silicide reaction will be non-uniform, leading to high contact resistance and potential void formation [T2]. The silicide depth must also be controlled: if it consumes too much silicon, the junction can be consumed entirely, causing a short to the substrate; if too shallow, the contact resistance remains high [T1].

The strain-relaxed buffer (SRB) concept from patent literature illustrates an extreme case of interface failure propagation: if the SiGe segment size exceeds the critical relaxation length, dislocations form that propagate through all subsequently grown layers into the channel [A2]. While this specific architecture is more relevant to FinFET generations, the principle — that SiGe defects propagate and degrade device performance — applies equally to the 28nm planar eSiGe stressor [P1].

A key directional tradeoff exists between strain enhancement and junction integrity [P1]. Increasing the Ge content in eSiGe increases the lattice mismatch and thus the compressive strain, improving mobility [P1]. However, higher Ge content also increases the risk of strain relaxation through dislocation formation, particularly if the thermal budget of subsequent steps is too high [A1]. The eSiGe volume also affects the source/drain resistance: a larger recess (more SiGe) means more strain but also a longer current path through the SiGe, which has higher resistivity than highly-doped silicon [P1].

Walk the Real Module

To see how these principles come together in the actual 28nm planar process sequence, you can Open SD Step 93 in the interactive flow [T3]. This step represents the point in the flow where the SD module's integration logic becomes concrete: the hardmask deposition, selective epitaxy, and gate protection converge into a single coherent sequence [T3].

At this step, the wafer carries the gate stack with first spacers already formed (Engineering Practice). The SiGe Hardmask SiN Deposition integration principles become apparent: the SiN layer is deposited conformally over the entire wafer, covering the gate, spacers, and active regions [T3]. This layer will subsequently be patterned to expose only the pFET source/drain areas for recess etch and eSiGe growth [P1]. The SiN hardmask deposition must achieve good step coverage and adhesion without introducing stress that could crack the underlying spacer or delaminate from the gate surface [T3].

The integration logic at this step reveals why the hardmask is SiN rather than oxide: SiN provides superior etch selectivity against the HF-based chemistries used for SiGe recess, and it also acts as a diffusion barrier during the high-temperature epitaxy and anneal steps [T3]. The SiN hardmask thus serves as a chemical, mechanical, and thermal protection layer simultaneously [P3].

Related Learning Paths

For engineers seeking to deepen their understanding of the 28nm planar integration, several adjacent topics provide complementary context:

• The 28nm Planar process flow overview provides the module-level map showing how the SD module fits within the complete FEOL sequence, from well formation through silicidation [T1].

• The 28nm Planar sidewall spacer integration process flow is directly upstream and governs the spacer dimensions that constrain the SD module's junction placement and strain transfer geometry [P1].

• The 28nm Planar well and channel implant integration process flow establishes the channel doping conditions that the SD module must complement without disrupting [T3].

Future Outlook

Looking beyond the 28nm planar node, the SD module's evolution follows two trajectories (Engineering Practice). First, the transition to FinFET architectures fundamentally changes the SD integration: the three-dimensional channel requires selective epitaxy on fin sidewalls rather than planar recesses, and the strain mechanisms shift from embedded stressors to the entire fin being strained [P2]. The single-sided source/drain extension implant schemes developed for FinFET SRAM [P2] illustrate how the planar SD module's lessons — gate protection, selective epitaxy confinement, and junction-to-spacer coupling — carry forward into new geometries.

Second, the strain engineering approaches pioneered at 28nm — embedded SiGe for pFET, SiN stress liners for nFET — continue to evolve [P1]. The strain-relaxed buffer concepts [A1][A2] represent a path toward higher Ge content channels without dislocation-mediated relaxation, potentially enabling mobility gains that exceed what embedded stressors alone can achieve. However, these approaches add process complexity and thermal budget constraints that must be carefully managed within the overall integration flow (Engineering Practice).

The fundamental integration logic — protect the gate, confine the epitaxy, control the junction, and transfer the strain — remains constant across nodes [T3]. What changes is the geometry and the available materials toolkit, but the causal mechanisms traced in this article continue to govern device performance at every generation [T3].