28nm Planar Source-Drain Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow

The source-drain (SD) module in the 28nm planar logic flow sits at a pivotal position within the front-end-of-line (FEOL) sequence. It receives a structure that has already undergone well and channel implantation, extension (lightly doped drain or LDD) implantation, and first spacer formation—steps that define the channel electrostatic framework and initial gate-edge offset. The SD module's responsibility is to complete the transistor's active terminal regions: forming deep source/drain junctions, introducing lattice stressors for channel mobility enhancement, and preparing the surface for self-aligned silicidation and subsequent contact formation.

In the 28nm planar node, this module delivers several critical device outcomes. First, it forms electrically active, shallow junctions that maintain short-channel control; junction depth and lateral diffusion directly influence drain-induced barrier lowering (DIBL) and subthreshold swing. Second, for pFET devices, it embeds silicon-germanium (SiGe) in the source/drain regions to induce compressive strain in the channel, boosting hole mobility. Third, it protects the gate stack throughout recess etch, epitaxy, and implantation steps. In a replacement gate flow, the high-temperature source/drain activation anneal is completed before metal gate deposition, avoiding threshold voltage shifts associated with thermal instability of the gate stack. [P2] Finally, the module produces a surface topography compatible with nickel or nickel-platinum silicidation, contact etching, and middle-of-line (MOL) contact metallization.

The SD module serves as the functional bridge between channel engineering and interconnect formation. Everything upstream—such as the 28nm Planar well and channel implant integration process flow—establishes the channel doping framework, while downstream modules depend on the junction profile, strain field, and interface quality that this module delivers. The overall 28nm Planar process flow relies on the SD module to balance junction scaling, stress engineering, and gate integrity.

Entry State and Sequence Logic

When the SD module begins, the wafer carries patterned gate stacks over active silicon regions enclosed by shallow trench isolation (STI). Extension implants have been introduced beneath the first spacer, defining the LDD offset. The entry topography consists of patterned gate lines with sidewall spacers hugging the gate edges.

The sequence logic of the 28nm SD module follows a strictly ordered set of operations:

1. SiGe hardmask deposition and patterning — A silicon nitride (SiN) hardmask is conformally deposited over the wafer and patterned to expose only the pFET source/drain regions while shielding the poly gate and nFET areas.
2. pFET source/drain recess and SiGe epitaxial growth — Isotropic or anisotropic wet etches (such as TMAH) create recessed cavities in pFET active regions, followed by selective epitaxial SiGe (eSiGe) growth to introduce uniaxial compressive strain.
3. Hardmask removal and clean — The protective SiN hardmask is selectively stripped without compromising the underlying sidewall spacers or dielectric isolation.
4. Deep source/drain ion implantation (N+ and P+) — High-dose implants define the deep junctions. For n-type source/drain regions, dopant species such as phosphorus or arsenic are introduced because both are highly soluble in silicon and can produce low sheet resistance. [T1] P-type regions receive high-dose boron or BF2 implants.
5. Thermal activation anneal — A rapid thermal anneal (RTA) or spike anneal activates dopants and repairs lattice damage while controlling dopant diffusion.
6. Silicide formation — A thin metal layer (nickel or nickel-platinum alloy) is deposited and reacted with exposed silicon/SiGe to form low-resistance silicide contacts.

The integration dependencies are strict. The SiN hardmask must precede SiGe recess and epitaxy to confine growth strictly to pFET source/drain areas. Poly gate protection is mandatory; exposing the polysilicon gate to recess etchants or epitaxy precursors degrades gate geometry, alters threshold voltage, and creates potential gate-to-source/drain shorting paths.

The connection to the preceding 28nm Planar sidewall spacer integration process flow is also vital. Spacer width determines the offset between the deep SD implant and the channel edge. If the spacer is too thin, dopants diffuse excessively into the channel, worsening short-channel effects; if too wide, parasitic series resistance increases and strain transfer efficiency from eSiGe drops.

Physical and Chemical Mechanisms

Strain Engineering via Embedded SiGe

The core physical mechanism in the 28nm pFET SD module is strain transfer from embedded SiGe to the silicon channel. Germanium has a larger atomic radius than silicon, giving SiGe a larger lattice constant. When SiGe is grown epitaxially inside recessed source/drain cavities adjacent to the channel, the lattice mismatch generates a longitudinal compressive strain field (Sxx) along the channel direction.

This compressive strain modifies the valence-band structure of the silicon channel by lifting the degeneracy between heavy-hole and light-hole bands. This reduces the hole effective mass along the transport direction and suppresses inter-valence-band scattering, directly increasing hole mobility and drive current (Ion).

Strain transfer efficiency depends heavily on the interface geometry. Wet etches using chemistries like TMAH expose specific crystallographic planes—such as (111) facets—creating angled cavity sidewalls. These faceted interfaces direct the compressive stress lines more effectively into the channel. Selective epitaxy kinetics rely on precursor chemistry (e.g., dichlorosilane and germane) where growth occurs rapidly on single-crystal silicon surfaces while chlorine additives (e.g., HCl) etch away unwanted nucleation on dielectric hardmasks and spacers.

Doping and Junction Formation

Deep source/drain junctions are formed by high-dose ion implantation. High-energy dopant ions penetrate the silicon lattice, coming to rest in a distribution characterized by a projected range and straggle. This energetic bombardment damages the crystalline lattice, creating amorphous regions.

The subsequent thermal anneal serves a dual purpose: recrystallizing amorphous silicon through solid-phase epitaxy and driving dopants into substitutional lattice sites where they become electrically active. The key challenge at the 28nm node is achieving full electrical activation while suppressing transient enhanced diffusion (TED). Spike annealing or rapid thermal processing achieves high peak temperatures with short dwell times to limit lateral junction encroachment into the channel.

In pFETs, the narrower bandgap of SiGe relative to silicon creates a favorable valence-band alignment at the source-channel interface, reducing the barrier height for hole injection and contributing to lower contact resistance.

Silicidation Chemistry

Silicidation forms a low-resistance ohmic interface between the semiconductor terminal and the metal contact. A thin nickel or nickel-platinum film is deposited across the wafer and subjected to a low-temperature anneal, causing a solid-state reaction with exposed silicon and SiGe to form nickel monosilicide (NiSi).

The reaction is self-aligned (salicide process) because metal reacts only where it directly touches exposed silicon or SiGe. Unreacted metal over dielectric spacers and STI oxide is selectively removed in wet chemical etches. Controlling silicon consumption during silicidation is critical: consuming too much silicon can penetrate the shallow junction boundary, leading to elevated substrate leakage current.

Interfaces and Failure Propagation

The SD module interfaces with upstream spacer/extension steps and downstream contact metallization. Deficiencies in the SD module propagate through predictable failure modes:

Upstream spacer interface: If the sidewall spacer suffers thinning or erosion during clean steps, deep SD implants penetrate too close to the channel edge. This causes junction encroachment, increasing gate overlap capacitance and worsening DIBL. Conversely, an excessively wide spacer increases series resistance and distances the eSiGe stressor from the channel, diminishing mobility gains.

Gate stack interface: The SiN hardmask must provide robust coverage over the poly gate. Pinholes or thin coverage allow TMAH etchant to attack the polysilicon gate during pFET cavity recess, causing gate height loss, threshold voltage variation, or silicide bridging shorts between the gate and source/drain.

SiGe epitaxy interface: Non-optimal epitaxy kinetics can cause surface roughness, crystalline defects, or strain relaxation through threading dislocations. Dislocations relax the compressive strain field and act as generation-recombination centers, significantly elevating reverse-bias junction leakage.

Downstream contact interface: Incomplete hardmask removal or non-uniform SiGe topography leads to localized silicide non-uniformity. This raises contact resistance and can cause contact spiking if silicide penetrates deep junction boundaries.

Trade-offs in this module require careful management. Increasing Ge concentration in eSiGe maximizes compressive strain and hole mobility, but elevates the risk of dislocation formation and strain relaxation. Deepening the S/D recess volume provides a larger stressor volume but increases parasitic resistance through the SiGe layer.

Walk the Real Module

To observe how these integration principles operate within the actual 28nm planar process sequence, you can Open SD Step 93 in the interactive flow.

At Step 93 (SiGe Hardmask SiN Deposition), the wafer carries patterned gate lines with first spacers intact. A conformal SiN layer is deposited over the entire surface. This step initiates the pFET strain integration sub-sequence by providing a durable chemical and physical shield.

Silicon nitride is chosen over silicon oxide because SiN demonstrates high chemical etch selectivity against HF-based cleans and alkaline wet etchants (such as TMAH) used during cavity recessing. Additionally, SiN acts as a robust barrier against oxygen and contaminant diffusion during high-temperature selective epitaxy.

Related Learning Paths

To further explore adjacent integration steps in the 28nm planar flow:

• The 28nm Planar process flow overview outlines the overall FEOL and MOL module sequence.
• The 28nm Planar sidewall spacer integration process flow details the spacer formation steps that define the source/drain implant offset.
• The 28nm Planar well and channel implant integration process flow describes the channel electrostatics established prior to SD processing.

Future Outlook

Beyond the 28nm planar node, source-drain integration evolved significantly with the transition to 3D transistor architectures. In FinFET nodes, planar S/D cavity recessing shifted to three-dimensional selective epitaxial growth on fin sidewalls (eSiGe for pFETs and phosphorus-doped Si/SiC for nFETs).

Despite architectural changes, the fundamental integration logic developed at 28nm—hardmask confinement, selective epitaxy kinetics, spacer-defined junction offsets, and self-aligned silicidation—remains essential for controlling contact resistance and channel strain in advanced logic manufacturing.