28nm Planar Contact Formation Process Flow: Integration Principles, Mechanisms, and Module Dependencies

Role in the Complete Flow

In the 28nm Planar process flow, the contact formation module occupies a pivotal position: it bridges the front-end-of-line (FEOL) transistor structures with the back-end-of-line (BEOL) metallization stack. By the time the flow reaches contact pattern execution, the silicon substrate already contains fully formed source/drain junctions with nickel silicide (NiSi) contact surfaces, gate electrodes—either polysilicon/SiON for low-power variants or high-k/metal gate (HKMG) structures built via replacement metal gate (RMG) integration—and isolation features such as shallow trench isolation (STI). The 28nm Planar process flow delivers a transistor whose active regions are electrically isolated and silicided, but not yet connected to any metal interconnect.

The contact module must deliver a set of electrically functional, physically reliable conductive pathways that penetrate through the first inter-layer dielectric (ILD0) and make ohmic contact to the underlying silicided source/drain and gate regions. These pathways—commonly called contact plugs—must exhibit low contact resistance, low junction leakage, and robust barrier performance against metal diffusion into silicon. Filling contact holes with tungsten plugs produces a smooth topography over the contact structure, resulting in a near-planar contact level prior to back-end-of-line metallization [T1]. Downstream, the BEOL multi-layer metallization depends entirely on the topography, planarity, and electrical quality that the contact module leaves behind. Any non-uniformity or resistive discontinuity introduced here propagates through every subsequent metal layer, degrading yield and device performance.

At 28nm, the contact module process flow is especially critical because it must accommodate two distinct integration flavors: a conventional polysilicon/SiON gate stack for low-power applications and a gate-last HKMG stack for high-performance mobile applications. In the HKMG variant, ILD0 deposition and planarization occur prior to replacement metal gate processing to encapsulate the dummy polysilicon gates. The 28nm Planar replacement metal gate integration process flow then executes, concluding with aluminum chemical mechanical polishing (Al-CMP) that defines the final metal gate height. Contact trench patterning and plug fill resume immediately following RMG completion, navigating the resulting topography with high fidelity.

Entry State and Sequence Logic

Upstream Dependencies

The entry state for contact formation is governed by precise chronological dependencies across surrounding modules. First, the 28nm Planar middle-of-line integration process flow completes silicide formation on source/drain and gate regions, establishing the low-resistance ohmic interface. Next, early CONTACT steps establish the dielectric matrix: ILD0 deposition—implemented as a deposited-etched-deposited (DED) sequence followed by high-aspect-ratio process (HARP) deposition—and ILD0 CMP planarize the dielectric to expose the top of the dummy gate structures.

In HKMG flows, the RMG module then takes over, replacing dummy polysilicon with the high-k dielectric and work-function metal stack, concluding with Al-CMP planarization. Once Al-CMP establishes the final metal gate topography, contact hole integration resumes. The ILD0 DED sequence narrows dielectric step-height variations across dense active regions, STI edges, and gate structures. A single blanket deposition would leave thick dielectric over dense active regions and thin dielectric over isolated gates, making simultaneous contact etch to all underlying nodes challenging. By depositing, partially etching back, and depositing HARP dielectric before RMG, the substrate provides a manageable thickness distribution when contact trench patterning starts post-RMG.

Sequence Logic Within the Contact Module

The internal sequence of the contact module follows a tightly constrained integration logic split across the RMG boundary:

1. ILD0 First Deposition and Etchback — Depositing the initial ILD0 dielectric layer and performing etchback to reduce step-height variation.
2. ILD0 HARP Fill and Planarization — Filling narrow gaps with HARP dielectric oxide and polishing flush via ILD0 CMP to prepare for gate replacement.
3. (RMG Module Intervention) — Dummy poly removal, HKMG stack deposition, and Al-CMP planarization.
4. Hardmask Stack Deposition — Depositing amorphous carbon, nitrogen-free DARC, and cap oxide layers to form a robust multi-layer hardmask for contact patterning.
5. Contact Lithography and Trench Etch — Patterning contact openings and performing anisotropic plasma etch through ILD0, stopping on silicide or gate cap surfaces.
6. Post-Etch Clean and Surface Treatment — Removing polymer residues, resputtered oxide, and photoresist, followed by nitrogen/hydrogen (N2H2) plasma treatment and pre-liner cleaning.
7. Integrated Liner/Barrier Deposition — Depositing titanium (Ti) adhesion layer and titanium nitride (TiN) diffusion barrier.
8. Tungsten (W) Fill — Chemical vapor deposition (CVD) of W to fill contact holes.
9. W CMP Planarization — Removing overburden W and barrier metal, leaving plugs flush with the ILD0 surface.

Each step's process window is bounded by both upstream topography and downstream requirements. For example, if the ILD0 DED sequence leaves excessive dielectric thickness variation, the post-RMG contact etch must over-etch significantly—risking silicide erosion—or accept incomplete openings at thicker dielectric regions. Similarly, the pre-liner clean must remove enough native oxide to establish low contact resistance without causing excessive junction damage.

Physical and Chemical Mechanisms

Contact Etch Chemistry and Selectivity

The contact etch through ILD0 is fundamentally a fluorocarbon-based plasma etch process. The chemistry involves a delicate balance between etching and polymerization: fluorine radicals generated from gases such as CHF3 react with SiO2 in the dielectric to form volatile SiF4 products, while carbon-rich polymer species deposit on sidewalls to provide anisotropy. The etch must exhibit high chemical selectivity toward the underlying silicide and gate cap materials, because dielectric thickness variation inherited from upstream steps means that some contacts reach silicide while others still have remaining dielectric to clear.

The physical mechanism of selectivity arises from the difference in chemical reactivity between SiO2 and the stopping layer. Silicon nitride (SiN) etch stop layers react more slowly with fluorocarbon plasmas because nitrogen-containing byproducts are less volatile than SiF4, creating a natural etch selectivity window. However, this selectivity is finite, and excessive over-etch to clear thick dielectric regions can erode the etch stop and expose the silicide to ion bombardment damage.

Barrier Layer Deposition Physics

The barrier and adhesion layer system—typically Ti followed by TiN—serves multiple physical functions. Titanium acts as an adhesion promoter and oxygen getter, reacting with residual native oxide on the silicide surface to form a thin TiSi2 interfacial layer that lowers the Schottky barrier height and promotes ohmic contact. TiN serves as a diffusion barrier, preventing tungsten from reacting with underlying silicon and blocking metal atom diffusion into the junction.

The deposition of these layers in contact holes is governed by geometric shadowing effects. Conventional physical vapor deposition (PVD) produces directional flux, leading to excessive deposition at the top of the contact hole and sparse coverage at the bottom and sidewalls. Ionized metal plasma (IMP) deposition addresses this by ionizing sputtered metal atoms in a plasma and accelerating them directionally toward the substrate, improving bottom coverage compared to conventional PVD.

Chemical vapor deposition (CVD) of TiN provides superior conformality because precursor molecules diffuse into the contact hole and react on surfaces isotropically, governed by surface chemical reaction kinetics rather than ballistic transport. Plasma-enhanced atomic layer deposition (PEALD) offers even more precise conformality through self-limiting surface reactions, where precursor adsorption saturates at a monolayer and plasma-activated reactants remove ligand groups in a separate step.

Tungsten CVD Fill Mechanism

The tungsten plug fill relies on CVD chemistry, typically using WF6 reduced by H2 or SiH4. The deposition proceeds through nucleation and bulk growth phases: initial nucleation on the TiN barrier surface must be dense and continuous to prevent void formation, and subsequent bulk growth must fill the contact hole from the bottom upward without creating seams or pinching off the opening prematurely. The conformal nature of CVD tungsten deposition is the primary reason W is preferred over aluminum for plug fill—CVD provides significantly better step coverage in confined geometries compared to PVD metals.

The nucleation kinetics are sensitive to the TiN surface condition. A rough or contaminated TiN surface can lead to sparse nucleation, creating isolated W islands that eventually coalesce with intervening voids. Conversely, a smooth, clean TiN surface promotes dense nucleation and void-free fill. This coupling between barrier layer quality and W fill integrity is a key integration principle: barrier deposition and tungsten CVD cannot be optimized independently.

Interfaces and Failure Propagation

ILD0–Silicide Interface

The interface between the ILD0 dielectric and the underlying silicide is the most failure-sensitive region in the contact module. During contact etch, any polymer residue or resputtered SiO2 left on the silicide surface creates a resistive barrier that increases contact resistance. The post-etch clean must remove both organic fluorocarbon polymers and inorganic oxide residues without attacking the silicide itself. An insufficient clean leaves a thin interfacial layer that acts as a series resistance element, while an overly aggressive clean can erode the silicide and expose bare silicon, increasing junction leakage.

The pre-liner clean and surface treatment performed just before titanium deposition physically removes residual oxide and contamination. However, excessive sputter etching can damage the shallow junction beneath the silicide, causing junction leakage to increase sharply. The tradeoff between oxide removal effectiveness and junction damage is a central tension in contact module integration.

Barrier–W Interface

The TiN barrier must provide continuous, pinhole-free coverage on all contact hole surfaces. Any discontinuity in the TiN layer allows WF6 precursor to penetrate to underlying Ti or silicon during tungsten CVD, causing "W encroachment"—uncontrolled tungsten growth into the junction region that disrupts device electrical characteristics. This failure mode is particularly insidious because it may not be detected by inline electrical testing and only manifests as reliability failures under thermal stress.

The barrier coverage challenge is directional: bottom coverage is critical for preventing W–silicon reactions, while sidewall coverage is critical for preventing lateral diffusion. IMP Ti improves bottom coverage through directional ion bombardment, but excessive Ti thickness can cause junction punch-through and stress concentration. CVD TiN provides better sidewall coverage but may exhibit higher impurity content than PVD alternatives, creating a tradeoff between conformality and film purity.

CMP–Topography Interface

To eliminate severe surface topography and enable subsequent photolithography within tight depth-of-focus windows, chemical mechanical planarization (CMP) is a unique technique that can provide excellent local and global planarity for ultra large scale integrated (ULSI) applications [P1]. The final W CMP step must remove all overburden tungsten and barrier metal while leaving plug material flush with the ILD0 surface. During chemical mechanical polishing of metal and dielectric films, 3-body contact caused by the pad surface asperities, slurry abrasives nanoparticles and the wafer surface lead to the uniform removal of material from the wafer surface [P5].

However, the CMP removal rate is pattern-dependent: dense contact arrays polish faster due to higher local pressure, while isolated contacts polish slower and may retain residual metal puddles. This pattern dependence creates across-chip variation in plug height and can cause topographic steps that propagate into the first metal layer deposition. Inserting dummy contact features in sparse regions regularizes local pattern density, reducing erosion in dense areas and dishing in isolated areas.

Gate Height Variation and Contact Etch Interaction

For 28nm HKMG flows, the Al-CMP step in the RMG module that defines the metal gate height introduces a critical coupling with subsequent contact etching. Non-uniform gate height—caused by aluminum dishing that increases with metal gate area and pattern density—directly affects the contact etch depth budget. If the gate is shorter than expected, the contact etch may penetrate through the gate cap and damage the gate dielectric. If the gate is taller, the dielectric thickness above the gate is reduced, creating a timing mismatch in the simultaneous etch to all nodes.

Walk the Real Module

To explore the actual step-by-step sequence of the 28nm Planar contact formation process flow, including the ILD0 DED first deposition and subsequent contact plug formation steps, you can Open CONTACT Step 150 in the interactive flow. This interactive view places each module step in its proper sequence context, showing how ILD0 deposition, hardmask coating, photolithography, contact etch, liner deposition, W fill, and CMP planarization steps chain together across the RMG boundary to form the complete contact structure.

The interactive flow also reveals critical handoff points: where the 28nm Planar middle-of-line integration process flow delivers the silicided substrate to the contact module, and where the contact module's CMP output becomes the entry surface for the first BEOL metal layer. Understanding these handoff points is essential for diagnosing cross-module defects—for example, a silicide quality problem originating in the MOL module may only manifest as elevated contact resistance measured after W plug formation, making root cause identification difficult without tracing the full sequence.

Directional Tradeoffs

Resistance–Leakage Tradeoff

The most fundamental directional tradeoff in the contact module is between contact resistance and junction leakage. Process variables that reduce contact resistance—deeper sputter etching, thicker Ti deposition, and aggressive silicide cleaning—tend to increase junction leakage by damaging the shallow source/drain junction. Conversely, conservative processing that protects the junction tends to leave interfacial oxide or contamination that raises contact resistance. The optimal operating point depends on device specifications: high-performance mobile (HPM) variants demand lower contact resistance and tolerate slightly higher leakage, while low-power (LP) variants prioritize leakage suppression.

Conformality–Purity Tradeoff

A second directional tradeoff exists between barrier layer conformality and film purity. CVD and ALD processes provide excellent step coverage in high-aspect-ratio contact holes but may incorporate impurities—such as chlorine, oxygen, or carbon—from precursor chemistry. PVD processes produce higher-purity films but suffer from poor conformality due to geometric shadowing. The 28nm contact module navigates this tradeoff by combining PVD Ti (for purity and adhesion) with CVD TiN (for conformal barrier coverage), accepting the complexity of a multi-technique stack to achieve both goals.

Planarity–Density Tradeoff

A third directional tradeoff involves CMP planarity and pattern density. Dense contact arrays achieve better ILD0 planarity through uniform CMP, but dense patterns increase local W plug density, which can increase capacitive coupling and RC delay. Sparse contact patterns reduce parasitic capacitance but create CMP non-uniformity that propagates as topographic variation into BEOL layers. Dummy fill insertion regularizes density but consumes layout area and can introduce parasitic capacitance near sensitive circuits.

Related Learning Paths

For engineers seeking to build a comprehensive understanding of the 28nm Planar integration scheme, several adjacent topics provide essential context:

• The 28nm Planar process flow overview situates the contact module within the complete FEOL-to-BEOL sequence, showing how each module's outputs constrain the next.
• The 28nm Planar middle-of-line integration process flow details silicide formation and strain engineering steps that immediately precede contact formation and define entry surface quality.
• The 28nm Planar replacement metal gate integration process flow explains Al-CMP and gate height control challenges that directly impact contact etch depth budgets in HKMG variants.

Engineers can also explore the interactive contact module flow to trace each step's position and dependencies in the full process sequence.

Future Outlook

While the 28nm Planar node represents a mature technology, the contact formation principles established here continue to evolve. Research into barrier-free ruthenium (Ru) contacts aims to eliminate the Ti/TiN barrier stack entirely, reducing effective contact dimension and series resistance for advanced nodes. Ru's low bulk resistivity, thermal stability, and native adhesion to dielectric surfaces enable direct contact to underlying silicide or metal source/drain regions without a separate diffusion barrier. However, barrier-free integration imposes stringent requirements on interface cleanliness and Ru nucleation uniformity, and long-term diffusion reliability under thermal stress remains under active study.

Plasma-enhanced ALD of Ta and Ti barriers, while originally proposed for highly scaled interconnects, continues to gain relevance as contact dimensions shrink and conformality requirements exceed PVD capabilities. The self-limiting reaction mechanism of ALD provides atomic-scale thickness control and excellent conformality, though impurity incorporation from metal chloride precursors remains a challenge that must be balanced against conformality gains.

Additionally, electrochemical dissolution mechanisms identified in silicon-containing resistive films during wet cleaning highlight the importance of electrical connection state control during post-patterning cleans—a principle that extends to contact module cleaning steps as well. Understanding these electrochemical failure modes becomes increasingly important as cleaning chemistries must remove ultra-thin contaminant layers without attacking shallow junctions.