28nm Planar Contact Formation Process Flow: Integration Principles, Mechanisms, and Module Dependencies

Role in the Complete Flow

In the 28nm Planar process flow, the contact formation module occupies a pivotal position: it bridges the front-end-of-line (FEOL) transistor structures with the back-end-of-line (BEOL) metallization stack [P1]. By the time the flow reaches this module, the silicon substrate already contains fully formed source/drain junctions with nickel silicide (NiSi) contact surfaces, gate electrodes—either polysilicon/SiON for low-power variants or high-k/metal gate (HKMG) structures built via replacement metal gate (RMG) integration—and isolation features such as shallow trench isolation (STI) [P1][T1]. The 28nm Planar process flow delivers a transistor whose active regions are electrically isolated and silicided, but not yet connected to any metal interconnect [T1].

The contact module must deliver a set of electrically functional, physically reliable conductive pathways that penetrate through the first inter-layer dielectric (ILD0) and make ohmic contact to the underlying silicided source/drain and gate regions [A1]. These pathways—commonly called contact plugs—must exhibit low contact resistance, low junction leakage, and robust barrier performance against metal diffusion into silicon [P2]. Downstream, the BEOL multi-layer metallization depends entirely on the topography, planarity, and electrical quality that the contact module leaves behind [P1]. Any non-uniformity or resistive discontinuity introduced here propagates through every subsequent metal layer, degrading yield and device performance [P1].

At 28nm, the CONTACT module process flow is especially critical because it must accommodate two distinct integration flavors: a conventional polysilicon/SiON gate stack for low-power applications and a gate-last HKMG stack for high-performance mobile applications [P1]. In the HKMG variant, the 28nm Planar replacement metal gate integration process flow concludes with aluminum chemical mechanical polishing (Al-CMP) that defines the final metal gate height, and the contact module must navigate the resulting topography with high fidelity [P1]. The ILD0 DED first deposition step provides the dielectric matrix through which contact holes are etched, making its integration principles foundational to the entire contact formation sequence [A1].

Entry State and Sequence Logic

Upstream Dependencies

The entry state for the contact module is defined by several preceding modules whose outputs collectively determine the contact module's process window (Engineering Practice). First, the 28nm Planar middle-of-line integration process flow completes with silicide formation on source/drain and gate regions, establishing the low-resistance interface that contacts must preserve [P2]. Second, for HKMG flows, the RMG module concludes with Al-CMP that planarizes the metal gate and leaves a gate height that directly constrains contact etch depth and alignment margins [P1]. Third, the ILD0 deposition—sometimes implemented as a deposited-etched-deposited (DED) sequence—creates the dielectric stack through which contact holes will be opened [A1].

The ILD0 DED first deposition integration principles are worth highlighting [P4]. The DED approach interleaves deposition and etch-back steps to manage topographic step heights across regions where gate features, STI edges, and active areas create dramatically different local dielectric thicknesses [T1]. A single blanket deposition would leave thick dielectric over dense active regions and thin dielectric over isolated gates, making simultaneous contact etch to all underlying nodes nearly impossible [P2]. By depositing, partially etching back to reduce step height variation, and then depositing again, the DED sequence narrows the thickness distribution that the contact etch must accommodate [P2]. This directly addresses the well-known challenge that dielectric thickness can vary by large factors across the chip, requiring extremely selective etch chemistry or multiple mask levels [T1].

Sequence Logic Within the Contact Module

The internal sequence of the contact module follows a tightly constrained logic:

1 (Engineering Practice). ILD0 final deposition and planarization — Completing the DED sequence and achieving a planar surface via CMP [P1]. 2. Contact lithography — Patterning contact openings with alignment to underlying gate and source/drain features [A3]. 3. Contact etch — Anisotropic plasma etch through ILD0, stopping on silicide or gate cap surfaces [P2]. 4. Post-etch clean — Removing polymer residues, resputtered oxide, and photoresist [P2]. 5. Pre-metal deposition clean — In-situ argon sputter etch or wet clean to remove native oxide on exposed silicide [P2]. 6. Barrier/adhesion layer deposition — Titanium (Ti) and titanium nitride (TiN) deposition [P2]. 7. Tungsten (W) fill — Chemical vapor deposition (CVD) of W to fill contact holes [P2]. 8. W CMP planarization — Removing overburden W and barrier layers, leaving plugs flush with the ILD0 surface [T1][A1].

Each step's process window is bounded by both upstream topography and downstream requirements (Engineering Practice). For example, if the ILD0 DED sequence leaves excessive thickness variation, the contact etch must either over-etch significantly—risking silicide damage—or accept incomplete opening at some locations [T1]. Similarly, the pre-deposition clean must remove enough native oxide to establish low contact resistance, but excessive sputter etch can damage the underlying junction and increase leakage [P2].

Physical and Chemical Mechanisms

Contact Etch Chemistry and Selectivity

The contact etch through ILD0 is fundamentally a fluorocarbon-based plasma etch process [P4]. The chemistry involves a delicate balance between etching and polymerization: fluorine radicals generated from gases such as $\text{CHF}_3$ react with $\text{SiO}_2$ in the dielectric to form volatile $\text{SiF}_4$ products, while carbon-rich polymer species deposit on sidewalls to provide anisotropy [T1]. The etch must be highly selective to the underlying silicide and gate cap materials, because the dielectric thickness variation inherited from upstream steps means that some contacts reach the silicide while others still have significant dielectric remaining [T1].

The physical mechanism of selectivity arises from the difference in chemical reactivity between $\text{SiO}_2$ and the stopping layer [T1]. Silicon nitride (SiN) etch stop layers, when present, react more slowly with fluorocarbon plasmas because the nitrogen-containing byproducts are less volatile than $\text{SiF}_4$, creating a natural etch selectivity window [P2]. However, this window is finite, and excessive over-etch to clear the thickest dielectric regions can erode the etch stop and expose the silicide to ion bombardment damage [T1].

Barrier Layer Deposition Physics

The barrier and adhesion layer system—typically Ti followed by TiN—serves multiple physical functions [P4]. Titanium acts as an adhesion promoter and oxygen getter, reacting with residual native oxide on the silicide surface to form a thin $\text{TiSi}_2$ interfacial layer that lowers the Schottky barrier height and promotes ohmic contact [T1][P2]. TiN serves as a diffusion barrier, preventing W from reacting with underlying silicon and blocking W diffusion into the junction [P2].

The deposition of these layers in high-aspect-ratio contact holes is governed by the geometric shadowing effect [P3]. Conventional physical vapor deposition (PVD) produces highly directional flux, leading to excessive deposition at the top of the contact hole and insufficient coverage at the bottom and sidewalls [P3][P4]. At 28nm, contact holes present modest but non-trivial aspect ratios that challenge conventional sputtering [P2]. Ionized metal plasma (IMP) deposition addresses this by ionizing the sputtered metal atoms in a plasma and accelerating them directionally toward the substrate, improving bottom coverage compared to conventional PVD [P2].

The fundamental coverage limitation of PVD arises from ballistic transport: deposited atoms travel in straight lines, and the trench geometry blocks flux from reaching sidewalls and bottoms [P3]. The maximum incidence angle that allows bottom deposition is determined by the aspect ratio geometry, with steeper walls creating narrower acceptance angles [P3]. Oblique-angle PVD with substrate rotation has been proposed as an alternative, tilting the incident flux to periodically illuminate sidewalls and bottoms, but this approach has limited applicability at higher aspect ratios [P3].

Chemical vapor deposition (CVD) of TiN provides superior conformality because the precursor molecules diffuse into the contact hole and react on surfaces isotropically, governed by surface chemical reaction kinetics rather than ballistic transport [P4]. Plasma-enhanced atomic layer deposition (PEALD) offers even more precise conformality through self-limiting surface reactions, where precursor adsorption saturates at a monolayer and plasma-activated reactants remove ligand groups in a separate step [P4]. PEALD enables continuous, dense barrier films at ultrathin dimensions, which is a physical necessity as contact dimensions shrink [P4].

Tungsten CVD Fill Mechanism

The W plug fill relies on CVD chemistry, typically using $\text{WF}_6$ reduced by $\text{H}_2$ or $\text{SiH}_4$ [P2]. The deposition proceeds through nucleation and bulk growth phases: initial nucleation on the TiN barrier surface must be dense and continuous to prevent void formation, and subsequent bulk growth must fill the contact hole from the bottom upward without creating seams or pinching off the opening prematurely [T1]. The conformal nature of CVD W deposition is the primary reason W is preferred over aluminum for plug fill—CVD provides significantly better step coverage in confined geometries compared to PVD metals [T1].

The nucleation kinetics are sensitive to the TiN surface condition [P2]. A rough or contaminated TiN surface can lead to sparse nucleation, creating isolated W islands that eventually coalesce with intervening voids [P2]. Conversely, a smooth, clean TiN surface promotes dense nucleation and void-free fill [P2]. This coupling between barrier layer quality and W fill integrity is a key integration principle: the barrier deposition and W deposition cannot be optimized independently [P2].

Interfaces and Failure Propagation

ILD0–Silicide Interface

The interface between the ILD0 dielectric and the underlying silicide is the most failure-sensitive region in the contact module [A1]. During contact etch, any polymer residue or resputtered $\text{SiO}_2$ left on the silicide surface creates a resistive barrier that increases contact resistance [T1]. The post-etch clean must remove both organic fluorocarbon polymers and inorganic oxide residues without attacking the silicide itself [P2]. An insufficient clean leaves a thin interfacial layer that acts as a series resistance element, while an overly aggressive clean can erode the silicide and expose bare silicon, increasing junction leakage [T1][P2].

The in-situ argon sputter etch performed just before Ti deposition serves as the final cleaning step, physically removing residual oxide and contamination [T1][P2]. However, this step introduces its own failure mode: excessive sputter etch can damage the shallow junction beneath the silicide, causing junction leakage to increase sharply [P2]. The tradeoff between oxide removal effectiveness and junction damage is a central tension in the contact module [P2].

Barrier–W Interface

The TiN barrier must provide continuous, pinhole-free coverage on all contact hole surfaces [P2]. Any discontinuity in the TiN layer allows $\text{WF}_6$ precursor to penetrate to the underlying Ti or silicon during W CVD, causing what is known as "W encroachment"—uncontrolled W growth into the junction region that disrupts the device's electrical characteristics [P2]. This failure mode is particularly insidious because it may not be detected by inline electrical testing and only manifests as reliability failures under thermal stress (Engineering Practice).

The barrier coverage challenge is directional: bottom coverage is most critical for preventing W–silicon reactions, while sidewall coverage is most critical for preventing lateral diffusion [P3]. IMP Ti improves bottom coverage through directional ion bombardment, but excessive Ti thickness can cause junction punch-through and stress concentration [P2]. CVD TiN provides better sidewall coverage but may exhibit higher impurity content than PVD alternatives, creating a tradeoff between conformality and film purity [P2].

CMP–Topography Interface

The final W CMP step must remove all overburden W and barrier metal while leaving the plug material flush with the ILD0 surface [P1]. The CMP removal rate is strongly pattern-dependent: dense contact arrays polish faster due to higher local pressure, while isolated contacts polish slower and may retain residual W "puddles" [P1]. This pattern dependence creates across-chip variation in plug height and can cause topographic steps that propagate into the first metal layer deposition [P2].

The coverage design rules and dummy fill strategies developed for CMP processes directly address this issue [P1]. By inserting dummy contact features in sparse regions, the local pattern density is regularized, reducing erosion in dense areas and dishing in isolated areas [P1]. At 28nm, cell-based dummy fill approaches were introduced, where the fill cell mimics transistor-level patterns to maintain consistent coverage across multiple layers simultaneously [P1].

Gate Height Variation and Contact Etch Interaction

For 28nm HKMG flows, the Al-CMP step that defines the metal gate height introduces a critical coupling with the contact module [P1]. Non-uniform gate height—caused by Al dishing that increases with metal gate area and pattern density—directly affects the contact etch depth budget [P1]. If the gate is shorter than expected, the contact etch may penetrate through the gate cap and damage the gate dielectric [P2]. If the gate is taller, the dielectric thickness above the gate is reduced, creating a timing mismatch in the simultaneous etch to all nodes [P2]. Dummy gate lines placed adjacent to metal gates help reduce this height loss, but the residual variation remains a contact module concern [P1].

Walk the Real Module

To explore the actual step-by-step sequence of the 28nm Planar contact formation process flow, including the ILD0 DED first deposition and subsequent contact plug formation steps, you can Open CONTACT Step 150 in the interactive flow [A1]. This interactive view places each module step in its proper sequence context, showing how the ILD0 deposition, contact lithography, etch, barrier deposition, W fill, and CMP planarization steps chain together to form the complete contact structure [P1].

The interactive flow also reveals the critical handoff points: where the 28nm Planar middle-of-line integration process flow delivers the silicided substrate to the contact module, and where the contact module's CMP output becomes the entry surface for the first BEOL metal layer [P1]. Understanding these handoff points is essential for diagnosing cross-module defects—for example, a silicide quality problem originating in the MOL module may only manifest as elevated contact resistance measured after W plug formation, making root cause identification difficult without tracing the full sequence [P2].

Interfaces and Failure Propagation: Directional Tradeoffs

Resistance–Leakage Tradeoff

The most fundamental directional tradeoff in the contact module is between contact resistance and junction leakage [P2]. Every process variable that reduces contact resistance—deeper sputter etch, thicker Ti, more aggressive silicide cleaning—tends to increase junction leakage by damaging the shallow source/drain junction [P2]. Conversely, conservative processing that protects the junction tends to leave interfacial oxide or contamination that raises contact resistance [P2]. The optimal operating point is a compromise that depends on the device's performance specification: high-performance mobile (HPM) variants demand lower contact resistance and can tolerate somewhat higher leakage, while low-power (LP) variants prioritize leakage suppression [P1].

Conformality–Purity Tradeoff

A second directional tradeoff exists between barrier layer conformality and film purity (Engineering Practice). CVD and ALD processes provide excellent step coverage in high-aspect-ratio contact holes but may incorporate impurities—oxygen, chlorine, or carbon—from precursor chemistry [P4]. PVD processes produce higher-purity films but suffer from poor conformality due to geometric shadowing [P3][P4]. The 28nm contact module navigates this tradeoff by combining PVD Ti (for purity and adhesion) with CVD TiN (for conformal barrier coverage), accepting the complexity of a multi-technique stack to achieve both goals [P2].

Planarity–Density Tradeoff

The third directional tradeoff involves CMP planarity and pattern density [P1]. Dense contact arrays achieve better ILD0 planarity through uniform CMP, but the dense pattern increases local W plug density, which can increase capacitance coupling and RC delay [P2]. Sparse contact patterns reduce parasitic capacitance but create CMP non-uniformity that propagates as topographic variation into BEOL layers [P1]. Dummy fill insertion regularizes the density but consumes area and may introduce parasitic elements near sensitive analog or RF circuits [P1].

Related Learning Paths

For engineers seeking to build a comprehensive understanding of the 28nm Planar integration scheme, several adjacent topics provide essential context:

• The 28nm Planar process flow overview situates the contact module within the complete FEOL-to-BEOL sequence, showing how each module's outputs constrain the next [P1].
• The 28nm Planar middle-of-line integration process flow details the silicide formation and strain engineering steps that immediately precede contact formation and define the entry surface quality [P1].
• The 28nm Planar replacement metal gate integration process flow explains the Al-CMP and gate height control challenges that directly impact contact etch depth budgets in HKMG variants [P1].

Engineers may also explore the interactive contact module flow to trace each step's position and dependencies in the full process sequence (Engineering Practice).

Future Outlook

While the 28nm Planar node represents a mature technology, the contact formation principles established here continue to evolve [P1]. Research into barrier-free ruthenium (Ru) contacts aims to eliminate the Ti/TiN barrier stack entirely, reducing effective contact dimension and series resistance for advanced nodes [A2][A3]. Ru's low bulk resistivity, excellent thermal stability, and native adhesion to dielectric surfaces enable direct contact to underlying silicide or metal source/drain regions without a separate diffusion barrier [A2]. However, barrier-free integration imposes stringent requirements on interface cleanliness and Ru nucleation uniformity, and long-term diffusion reliability under thermal stress remains under investigation [A3].

Plasma-enhanced ALD of Ta and Ti barriers, while originally proposed for highly scaled interconnect, continues to gain relevance as contact dimensions shrink and conformality requirements exceed what PVD can deliver [P4]. The self-limiting reaction mechanism of ALD provides atomic-scale thickness control and excellent conformality, but impurity incorporation from metal chloride precursors remains a challenge that must be balanced against conformality gains [P4].

Additionally, electrochemical dissolution mechanisms identified in silicon-containing resistive films during wet cleaning highlight the importance of electrical connection state control during post-patterning cleans—a principle that may extend to contact module cleaning steps as well [A1]. Understanding these electrochemical failure modes becomes increasingly important as cleaning chemistries must remove ever-thinner contaminant layers without attacking ever-shallower junctions [P1].