28nm Planar Replacement Metal Gate Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow

The 28nm planar replacement metal gate (RMG) integration is a pivotal module that sits between front-end-of-line (FEOL) transistor formation and back-end-of-line (BEOL) interconnect construction [P4]. In the broader 28nm Planar process flow, the RMG module receives a partially completed transistor structure in which a dummy poly silicon gate has already been patterned, spacer-defined, and electrically integrated with source/drain regions [P3]. The module's fundamental mission is to remove that sacrificial gate material and replace it with a high-k dielectric and metal gate stack that delivers the final work function and threshold voltage characteristics required for device operation [P2].

The upstream boundary of the RMG module is defined by the completion of pre-metal dielectric (PMD) deposition and PMD chemical mechanical polishing (CMP), which planarizes the dielectric surface and exposes the top of the dummy poly silicon gate [P1]. At this entry point, the transistor channel, source/drain implants, and stress engineering features are already in place and have undergone their high-temperature activation anneals [P2]. The downstream deliverable is a fully formed high-k/metal gate stack with the correct effective work function (EWF) for both NMOS and PMOS devices, a planarized gate surface suitable for contact formation, and a stable interface that will not drift during subsequent BEOL thermal cycles [P4].

A critical reason the RMG approach was adopted at 28nm is that it decouples the high-k dielectric from the high-temperature dopant activation steps [P4]. In a gate-first approach, the high-k/metal gate stack must survive rapid thermal annealing (RTA) for dopant activation, which can cause crystallization of the high-k layer and undesirable chemical reactions between the metal gate and the dielectric, such as boron diffusion into HfO₂ [P2]. By deferring the real gate stack formation until after activation, the RMG module preserves the amorphous nature of the high-k and maintains tight threshold voltage control [P4].

Entry State and Sequence Logic

When the RMG module begins, the wafer has already traversed a long sequence of FEOL steps: well formation, channel doping, gate oxide growth, dummy poly silicon deposition, gate patterning, spacer formation, source/drain epitaxy or implantation, and dopant activation anneal [P4]. The dummy gate stack at this stage typically consists of a sacrificial gate oxide (SiO₂ or SiON), a poly silicon layer, and possibly a hardmask cap — all serving as a structural placeholder that defines the gate footprint and protects the channel during upstream processing [P3].

The integration sequence logic of the 28nm RMG module process flow proceeds through several well-ordered phases:

1 [P4]. PMD planarization and dummy gate exposure: PMD dielectric is deposited over the completed FEOL structure and polished back by CMP to expose the poly silicon dummy gate [P3]. The quality of this CMP step — measured in within-die and within-wafer uniformity — directly determines whether the subsequent dummy poly remove step encounters a uniform starting surface [P1].

2. Dummy poly remove: The sacrificial poly silicon is selectively etched away, leaving an open trench defined by the gate spacers and the underlying dielectric or high-k stack [P3]. This step can be accomplished through wet etching (using tetramethylammonium hydroxide, TMAH) or dry etch approaches, each with distinct selectivity and residue considerations [P3].

3. High-k and interfacial layer deposition: In the high-k-first variant, the high-k dielectric is already present beneath the dummy gate and protected by an etch stop layer (ESL) during removal [P3]. In the high-k-last variant, the high-k is deposited after dummy gate removal, typically by atomic layer deposition (ALD) for conformality [P4].

4. Work function metal deposition: One or more metal layers (such as titanium nitride, TiN, for PMOS or titanium-aluminum, TiAl, for NMOS) are deposited to set the effective work function [P4]. The layer count, composition, and oxidation state collectively tune the EWF [P4].

5. Fill metal deposition and CMP: A low-resistivity metal (such as aluminum or tungsten) fills the remaining trench, and a final CMP removes excess metal to produce a planar gate surface ready for 28nm Planar contact formation process flow [P2].

The sequential dependency is strict: each phase must achieve its selectivity and uniformity targets before the next phase can proceed, because residual material or dimensional variation propagates irreversibly through the stack [P1].

Physical and Chemical Mechanisms

Dummy Poly Removal Chemistry

The dummy poly remove step is governed by fundamentally different mechanisms depending on whether a wet or dry approach is employed [P3]. In the wet approach using TMAH, hydroxide ions (OH⁻) nucleophilically attack the silicon-silicon bonds on the poly silicon surface, forming soluble silicate intermediates and releasing hydrogen gas [P3]. This reaction is surface-reaction-limited and exhibits pronounced crystallographic anisotropy: the <111> orientation, with its higher atomic density and more stable surface structure, etches significantly more slowly than other orientations [P1]. This anisotropy becomes a critical integration concern because the crystal orientation of the poly silicon is influenced by the underlying dielectric layer — poly silicon on nitrogen-containing dielectrics such as SiON or TiN tends to form <111> preferentially, creating residue risk [P3].

The Dummy Poly Dry Removal integration principles center on plasma-based etching, where fluorine- or chlorine-based chemistries react with silicon to form volatile products [P3]. The dry etch approach offers anisotropic profile control and avoids the capillary forces associated with liquid-phase processing, which is particularly relevant for high-aspect-ratio gate trenches where pattern collapse is a concern [P2]. However, dry etch introduces plasma-induced damage risks and may exhibit lower selectivity to underlying dielectric or metal layers [P3].

High-k Deposition and Interface Formation

In the high-k-last RMG variant, the interfacial layer (typically SiO₂) and the high-k dielectric (typically HfO₂) are deposited by ALD after dummy gate removal [P4]. ALD provides self-limiting, layer-by-layer growth that ensures conformal coverage within the gate trench, even as trench dimensions scale narrower [P2]. The physical mechanism involves sequential, self-terminating surface reactions: a precursor pulse adsorbs and reacts with surface hydroxyl groups, followed by a purge and an oxidant pulse that completes the monolayer [P1]. This cycle repeats until the desired film thickness is achieved (Engineering Practice).

The quality of the high-k/interfacial layer interface is paramount because it determines the equivalent oxide thickness (EOT), gate leakage, and threshold voltage stability [P4]. Defects at this interface — including oxygen vacancies, suboxide states, and interfacial roughness — create charge traps that cause threshold voltage instability and degrade channel mobility [P4].

Work Function Metal Physics

The effective work function of the metal gate stack is not simply the vacuum work function of the deposited metal [P4]. It is jointly determined by the metal's Fermi level, interfacial dipoles at the metal/high-k boundary, and the oxidation state of the metal layers [P4]. For PMOS, TiN is commonly used, and its work function can be modulated by increasing the layer thickness and controlling oxidation — oxygen incorporation at the TiN/HfO₂ interface modifies the interfacial dipole, shifting the EWF toward the valence band edge [P4]. For NMOS, TiAl provides a low work function, but aluminum is a fast-diffusing species that can penetrate TiN and create defects in HfO₂, especially under prolonged thermal treatment [P4].

From a device physics perspective, the metal gate work function directly sets the threshold voltage through the flat-band voltage relationship [T2]. The MOSFET threshold voltage depends on the gate work function relative to the semiconductor Fermi level, the oxide charge, and the channel doping [T2]. By engineering the work function metal stack rather than relying solely on channel doping, the RMG module achieves simultaneous optimization of threshold voltage, mobility, and leakage — a balance that becomes increasingly difficult with conventional doping alone as devices scale [T2].

CMP Mechanisms in RMG

The final CMP step that planarizes the fill metal is governed by the synergistic interaction of chemical softening and mechanical abrasion [P1]. For oxide CMP, the Langmuir–Hinshelwood framework describes surface hydroxylation and oxidizer adsorption as rate-controlling steps [P1]. The removal rate depends on the balance between chemical reaction at the surface and mechanical wear by slurry particles [P1]. In the RMG context, CMP must simultaneously remove the fill metal and stop on the PMD dielectric — a selectivity requirement that becomes more stringent as gate dimensions shrink and the risk of gate resistance variation, poor gate fill, or raised source/drain exposure increases [P1].

Interfaces and Failure Propagation

The RMG module is characterized by multiple material interfaces, each of which represents a potential failure propagation path [P4]. Understanding these interfaces and their directional tradeoffs is essential for process integration (Engineering Practice).

PMD-to-Dummy Gate Interface

The uniformity of PMD CMP directly governs the exposure height of the dummy poly silicon gate [P3]. If CMP over-polishes locally, the dummy gate top is recessed below the PMD surface, leading to incomplete gate trench opening during dummy poly remove and potentially causing poor metal fill [P3]. If CMP under-polishes, residual dielectric remains on the gate, blocking the etch and leaving poly silicon residues that occupy the space intended for the high-k and metal gate [P1]. This failure mode propagates downstream as increased gate resistance, threshold voltage shifts, or outright device failure [T2].

Dummy Poly-to-Underlayer Interface

The interface between the dummy poly silicon and the underlying dielectric (SiO₂, SiON, TiN, or ESL) is where etch selectivity is tested [P3]. Wet TMAH etching achieves high selectivity to SiO₂ but may leave residues on SiON or TiN underlayers due to crystallographic orientation effects [P3]. In the high-k-first RMG variant, an ESL protects the high-k during dummy gate removal — if the ESL is compromised, the high-k is exposed to etch chemistry and may be thinned or damaged, increasing EOT and gate leakage [P4].

High-k-to-Work Function Metal Interface

The interface between the high-k dielectric and the work function metal is thermodynamically unstable under certain conditions [P4]. Aluminum diffusion from TiAl through TiN into HfO₂ occurs rapidly during thermal treatment, creating oxygen vacancies and fixed charge that shift the EWF toward mid-gap [P4]. This drift reduces the NMOS/PMOS threshold voltage separation, degrading the on/off current ratio and increasing static power consumption [T2]. The directionality of this tradeoff is clear: higher thermal budgets worsen Al diffusion, narrowing the process window for NMOS work function stability [P4].

Metal Gate-to-Contact Interface

Downstream of the RMG module, the planarized metal gate surface must support reliable contact formation in the 28nm Planar metal-one interconnect integration process flow [P4]. Gate height non-uniformity from CMP variation propagates into contact resistance variation, because the contact etch must land on the gate metal without punching through into the channel [P2]. Dishing or erosion during metal CMP creates local recesses that can cause open contacts or high-resistance connections [P1].

Failure Mode Summary

The dominant failure modes in 28nm RMG integration — poly silicon residue, work function drift, CMP dishing/erosion, and gate resistance variation — all share a common root cause: the loss of selectivity or uniformity at one interface, which propagates irreversibly through subsequent steps [P4]. Because the RMG module is a sequential, non-correctable flow, there is no rework path once a failure is embedded [P1, P3].

Walk the Real Module

To ground these principles in the actual 28nm planar process, the interactive flow provides a step-by-step walkthrough of the RMG module [P4]. The sequence begins with PMD planarization exposing the dummy gate, proceeds through dummy poly remove, high-k and metal gate deposition, and concludes with fill metal CMP [P3].

You can explore the detailed sequence starting from Open RMG Step 155 in the interactive flow, which illustrates the transition from dummy gate exposure to the subsequent deposition and planarization steps [P3]. Walking through the interactive flow alongside the mechanism descriptions above provides an integrated understanding of how each physical and chemical principle maps onto a concrete process step (Engineering Practice).

The key insight from the interactive flow is that the RMG module is not a collection of independent unit processes — it is a tightly coupled sequence where each step's output becomes the next step's input, and where selectivity, uniformity, and cleanliness requirements compound rather than reset (Engineering Practice). This coupling is why the 28nm replacement metal gate integration demands cross-module optimization rather than isolated recipe tuning [P1, P3].

Related Learning Paths

To build a comprehensive understanding of the 28nm planar integration, several adjacent topics provide valuable context:

• The 28nm Planar process flow overview provides the full-module context in which the RMG module operates, showing how FEOL steps upstream define the constraints that RMG must satisfy [P4].
• The 28nm Planar contact formation process flow explains the immediate downstream consumer of the RMG module's output, where gate surface quality and topography directly impact contact resistance and yield [P4].
• The 28nm Planar metal-one interconnect integration process flow extends the chain further into BEOL, where the planarized gate and contact structures form the foundation for the first metal interconnect layer [P2].

These articles collectively trace the integration thread from transistor formation through gate replacement to interconnect construction, providing a complete picture of the 28nm planar technology node [P2].

Future Outlook

While the 28nm planar node remains a workhorse technology for many product categories, the RMG integration principles established at this node have evolved significantly in subsequent generations [P4]. The transition from planar MOSFETs to FinFET and then to gate-all-around (GAA) architectures has extended the RMG concept to three-dimensional structures, where the dummy poly remove step becomes even more challenging due to the need to clear narrow, steep trenches without residue [P2].

Research directions include gas-phase etching (GPE) to eliminate pattern collapse risk associated with liquid-phase processing, novel work function metal systems that resist thermal diffusion, and CMP selectivity enhancement through pre-polish surface modification techniques such as ion implantation [P1, P2]. The CFET architecture, which vertically stacks NMOS and PMOS devices, further complicates RMG by requiring gate isolation and sharing schemes that were not needed in planar flows [A1, A2].

For engineers working on 28nm planar technology, understanding the RMG module's principles provides a transferable foundation: the selectivity logic, interface management, and sequential dependency concepts apply directly to more advanced nodes, even as the geometric complexity increases [P4]. The core lesson — that integration is governed by the propagation of interfaces through a non-correctable sequence — remains valid regardless of the specific device architecture [P2].