28nm Planar FlowPreview

he integrity of surrounding dielectrics and spacers [A1]. The prior ILD0 deposition and CMP expose the top of the dummy polysilicon, but leave it laterally confined by oxide, making a purely wet removal kinetically limited and prone to non-uniform penetration without an initial dry opening step [P1]. By partially or fully removing the exposed portion of dummy polysilicon using a directional dry etch, this step establishes an accessible reaction front for the subsequent wet removal, ensuring continuity of the replacement gate cavity and preventing trapped poly remnants that would otherwise shadow the wet etchant [P1]. The existence of this step therefore directly conditions the success of the downstream wet etch and metal gate fill, which are highly sensitive to residual silicon in the gate trench [A1]. From a device-physics perspective, complete removal of the dummy gate is mandatory to enable replacement by a metal gate with well-defined work function and minimal parasitic capacitance, which in turn governs threshold voltage control and short-channel behavior in planar MOSFETs [T1]. Any residual polysilicon left behind would reintroduce polysilicon depletion and Fermi-level pinning effects, degrading electrostatic gate control and increasing effective oxide thickness [T1]. Thus, this dry removal step is not merely a cleaning operation but an enabling step for achieving the intended electrical behavior of the 28 nm planar device architecture [P1].

Physical and Chemical Mechanism

Dummy Poly Dry Removal relies on plasma-assisted silicon etching, where halogen radicals generated in the plasma chemically react with silicon atoms at the polysilicon surface to form volatile silicon halide species, which are then desorbed into the gas phase [P3]. The etch proceeds through a synergistic mechanism in which chemical reaction probability is enhanced by ion bombardment that breaks Si–Si bonds and removes passivation layers, making the process inherently anisotropic and directionally controllable [P3]. This directionality is essential to preferentially clear the vertical gate opening while minimizing lateral attack on ILD oxides and spacers that define the gate length (Engineering Practice). At the microscopic level, the reaction rate is governed by surface-reaction-limited kinetics rather than bulk diffusion, meaning that exposed silicon area and surface condition dominate etch uniformity [P3]. Plasma conditions that increase ion energy tend to enhance physical sputtering components, which can accelerate silicon removal but simultaneously raise the risk of dielectric damage and charge injection into underlying gate oxides [T1]. Consequently, the dry etch is typically designed to stop on or near dielectric interfaces, leaving a controlled residual thickness that can be safely and selectively removed by the subsequent wet process, which operates via a fundamentally different chemical pathway [P1].

Material and Method Selection Logic

A dry etch method is selected for the first stage of dummy poly removal because plasma-based processes offer superior directionality and pattern fidelity compared with purely chemical wet etches, especially when the sacrificial material is embedded within a high-aspect-ratio dielectric cavity [P3]. Polysilicon is particularly well suited to halogen-based plasma removal because its reaction products are volatile at process temperatures, enabling efficient material evacuation without redeposition under properly balanced plasma conditions [P3]. In contrast, underlying SiO₂- or SiON-based dielectrics form non-volatile halides and therefore exhibit inherently higher etch resistance, providing the selectivity required at this stage [P1]. Key process parameters interact in well-understood directions: increasing ion energy or flux enhances etch anisotropy and rate, while increasing the relative contribution of neutral radicals favors chemical selectivity over physical damage [P3]. Similarly, chamber wall conditions influence steady-state radical densities through adsorption and re-etching phenomena, which can indirectly affect wafer-level uniformity if not tightly controlled [P3]. For this reason, process monitoring focuses on endpoint detection and plasma stability rather than absolute etch depth, since the objective is to create an open, continuous cavity rather than to meet a dimensional target (Engineering Practice).

Node-Specific Considerations for 28 nm Planar Technology

In 28 nm planar CMOS, gate lengths are sufficiently short that even small residuals of dummy polysilicon can translate into significant variability in effective channel length and threshold voltage [T2]. At the same time, gate oxides are thin enough that plasma-induced damage or charging during aggressive dry etching can measurably degrade interface quality and carrier mobility [T1]. The split between dry and wet dummy poly removal therefore reflects a node-specific compromise: the dry step provides geometric access and profile control, while the wet step completes silicon removal with minimal damage through surface-reaction-dominated chemistry [P1]. This hybrid strategy is consistent with integration schemes described in replacement-gate patents, where dry and wet etches are deliberately combined to balance profile control, selectivity, and device reliability [A1].