28nm Planar Metal-One Interconnect Integration: Process Flow Principles and Integration Logic

Role in the Complete Flow

The metal-one (M1) interconnect module in the 28nm planar technology node occupies a pivotal position in the back-end-of-line (BEOL) sequence: it is the first metal layer that connects to the front-end-of-line (FEOL) device structures through silicided source/drain and gate contact plugs. In the 28nm planar process flow, the M1 module receives a wafer on which transistor formation—including high-k/metal-gate stack engineering, source/drain implantation, activation anneals, and silicide formation—has been completed. The surface topography entering M1 is defined by the contact etch stop layer (CESL) and the pre-metal dielectric (PMD) stack, whose planarization quality governs the photolithographic depth of focus (DOF) available for M1 trench patterning.

Downstream, the M1 module delivers a planarized, electrically functional first-level interconnect network that distributes signals and power from individual transistor contacts to higher-level routing layers. Every subsequent metal layer—starting from 28nm Planar metal-two interconnect integration—depends on the M1 surface being sufficiently flat for reliable damascene patterning, and on the M1-to-contact interfaces being robust enough to prevent electromigration and contact resistance drift. The M1 module acts as both an electrical bridge and a topographic baseline: it translates discrete device terminals into a routable routing grid while providing the foundation upon which the BEOL stack is constructed.

The 28nm M1 integration is distinct because it resides directly at the transition between front-end device physics and back-end metallization. Contact resistance at the contact plug interface, dielectric gap fill around narrow features, and chemical mechanical planarization (CMP) dishing and erosion interact closely, influencing both low-frequency signal speed and long-term reliability.

Entry State and Sequence Logic

Upstream Dependencies

When the M1 module begins, the wafer has completed the full FEOL sequence characteristic of the 28nm planar flow. The gate stack has been patterned, source and drain regions have been implanted and activated, and nickel silicide contacts have been formed to establish low-resistance electrical connections to silicon. A conformal CESL—typically silicon nitride—covers the gate topography, followed by a PMD dielectric stack (such as oxide deposited by chemical vapor deposition) that fills gaps between active structures.

The contact module precedes M1: contact holes are etched through the PMD and CESL, barrier layers are deposited, tungsten plugs are filled, and tungsten CMP planarizes the surface. For high aspect ratio contact structures, chemical vapor deposition of titanium nitride achieves substantially higher bottom coverage than physical vapor deposition techniques such as ionized metal plasma titanium [P1]. The integrity of this incoming surface—its global and local planarity, freedom from tungsten plug erosion, and low contact resistance—defines the starting conditions for M1 dielectrics.

M1 Module Sequence Logic

The 28nm M1 module follows a single-damascene integration scheme utilizing a hard mask architecture and low-k inter-level dielectric (ILD) films. The detailed sequence consists of discrete deposition, lithography, etch, plating, and planarization steps:

1. High-Resolution TEOS Base Oxide Deposition: An initial oxide layer is deposited over the contact surface to normalize surface chemistry, dangling bond density, and -OH termination before main dielectric deposition.
2. Stress-Relief and Protection Layer Stack: Layers such as TiN and stress-managed SiN are deposited and patterned to relieve film stress and define underlying alignment or hard mask features.
3. ILD Low-k Dielectric Stack: The primary M1 ILD is deposited, incorporating nitrogen-doped carbide (NDC) diffusion barriers, carbon-doped low-k dielectrics, and ultraviolet (UV) curing to drive out organic solvents and enhance mechanical stability.
4. Hard Mask Stack Deposition: Buffer layers, metal hard masks (such as TiN), and capping oxides are sequentially deposited to prepare for narrow trench patterning.
5. Photolithography and Hard Mask Etching: Deep ultraviolet (DUV) lithography patterns the M1 trenches, followed by dry reactive ion etching (RIE) to transfer the pattern into the hard mask stack.
6. Trench Etching and Clean: Diluted hydrofluoric acid (DHF) and wet chemical cleans remove polymer residues and etch the trenches into the low-k dielectric down to the underlying contact plugs.
7. Metallization (Barrier/Seed/Plating): A Ta/TaN diffusion barrier is deposited to prevent copper migration into the low-k dielectric, followed by a PVD copper seed layer and copper electrochemical plating (ECP) to achieve bottom-up fill.
8. Bevel Clean and CMP: Bevel etching removes extraneous copper from the wafer edge, and copper CMP polishes excess copper and barrier metal, stopping on the dielectric surface to isolate the M1 wires.

This explicit sequence ensures that structural stress, lithographic reflection, and trench etching profile are controlled before copper deposition.

Physical and Chemical Mechanisms

TEOS Oxide Deposition and Conformality

In TEOS-based chemical vapor deposition, the reactive intermediate species tend to exhibit low sticking coefficients on the order of 0.1, which enhances precursor surface migration prior to bonding [T1]. This surface mobility allows TEOS-derived species to migrate into localized micro-depressions and step features before chemisorbing, producing significantly better step coverage than traditional silane-based oxide deposition.

Because the reaction is surface-reaction-limited, variations in surface hydrophilicity, dangling bond density, or residual -OH termination can modulate local deposition rates and film microstructure. The initial HR TEOS oxide deposition intentionally normalizes these surface chemical state variations across heterogeneous regions (such as tungsten plugs, residual oxides, and modified interfaces), creating a uniform nucleation foundation before bulk ILD growth.

Damascene Trench Etching and Barrier Formation

Pattern transfer into the M1 ILD requires high anisotropic selectivity. Fluorocarbon plasma chemistry (CxFy / Ar / N2) etches the carbon-doped low-k film while preserving the metal hard mask sidewalls. Etch profile control is essential: vertical or slightly tapered sidewalls facilitate continuous barrier and seed layer coverage, whereas re-entrant profiles cause overhangs during Ta/TaN PVD deposition, leading to voids during copper electroplating.

The Ta/TaN bilayer serves two distinct roles: TaN provides strong adhesion to the oxide/low-k dielectric sidewalls, while metallic Ta offers a favorable interface for copper seed nucleation. The thickness of this barrier represents a fundamental trade-off: a thinner barrier increases the effective cross-sectional area of copper (reducing line resistance), but increases the risk of local barrier breakdown, which leads to copper diffusion into the low-k dielectric and inter-line leakage.

Copper Electroplating and Chemical Mechanical Planarization

Copper fill in single-damascene M1 trenches relies on super-conformal electrochemical plating driven by organic bath additives (accelerators, suppressors, and levelers). Accelerators accumulate at trench bottoms, enhancing localized deposition rates, while suppressors adsorb at top corners to prevent premature seam formation. This bottom-up fill mechanism yields void-free copper lines.

Following plating, chemical mechanical planarization removes overburden copper and the underlying barrier layers. CMP operates through combined chemical oxidation and mechanical abrasion: the polishing slurry passivates copper surfaces, while the mechanical action of the polishing pad selectively removes passivated material from high spots. Over-polishing must be minimized to prevent copper dishing (receding of copper centerlines) and dielectric erosion, both of which degrade sheet resistance uniformity and degrade the planar baseline for subsequent upper metal layers.

Interfaces and Reliability Mechanisms

M1-to-Contact Interface Stability

The contact plug to M1 interface is a primary contributor to total parasitic resistance in advanced logic circuits. Because M1 copper cannot directly touch tungsten due to adhesion and diffusion issues, the Ta/TaN barrier mediates this connection. Cleanliness of the tungsten plug surface prior to barrier deposition is critical; native oxide or organic residues at the bottom of the M1 trench dramatically increase contact resistance and introduce high variability.

Dielectric Integrity and Low-k Porosity

While non-plasma TEOS and ozone processes yield good step coverage, the resulting films are typically more porous than silane-based or plasma-enhanced TEOS oxides and absorb more moisture [T1]. Moisture uptake in inter-level dielectrics increases the effective dielectric constant (k-value) and creates free hydroxyl radicals (-OH) that accelerate copper electromigration and time-dependent dielectric breakdown (TDDB).

To mitigate this, the 28nm M1 integration stack incorporates denser nitrogen-doped carbide (NDC) capping layers and subjects the low-k films to post-deposition UV curing. This curing process reconstructs the Si-O-Si backbone while cross-linking methyl groups, restoring mechanical strength and dielectric breakdown resistance.

Downward and Upward Defect Propagation

Defects originating in M1 propagate in both directions:

• Upward Propagation: Excessive CMP dishing or dielectric erosion generates topography that degrades the depth of focus for subsequent metal-two photolithography steps, leading to line-width variation or bridging faults.
• Downward Propagation: Over-etching during M1 trench RIE can punch through the PMD, eroding underlying tungsten plugs or damaging the underlying CESL and gate structures. Furthermore, unpassivated plasma damage can introduce fixed charges that shift transistor threshold voltages.

Walk the Real Module

To explore the exact step sequence of the 28nm Planar M1 interconnect module—including the HR TEOS Oxide Deposition step and its position relative to hard mask patterning and copper CMP—you can Open M1 Step 168 in the interactive flow.

Tracing the steps interactively illustrates how early surface preparation and hard mask deposition dictate the outcome of high-aspect-ratio trench etching and electroplating, illustrating the integration logic that secures both high yield and stable electrical performance.

Related Learning Paths

To broaden your understanding of BEOL integration and surrounding modules, consider exploring these related guides:

• 28nm Planar process flow overview: Provides global context on how FEOL, contact, M1, and upper metal modules connect across the entire fabrication sequence.
• 28nm Planar replacement metal gate integration process flow: Details the gate-last high-k/metal-gate sequence and silicide module that precede contact plug and M1 formation.
• 28nm Planar metal-two interconnect integration: Covers the transition from single-damascene M1 to dual-damascene V1/M2 processing and higher-level routing challenges.