28nm Planar Metal-Two Interconnect Integration: Process Flow Principles and Mechanism Deep Dive

Role in the Complete Flow

The 28nm Planar metal-two (M2) interconnect integration module occupies a pivotal position in the back-end-of-line (BEOL) sequence of a 28nm planar CMOS process. By the time the wafer enters the M2 module, the front-end-of-line (FEOL) transistor structures — including high-k/metal gate (HKMG) or poly-SiON gate stacks depending on the platform variant — have been fully formed, and the contact module has established the electrical bridge between the silicon channel and the lower interconnect stack. The 28nm Planar process flow has already produced the metal-one (M1) layer, which routes local signals and power rails above the contact plugs. Intermetal dielectrics are deposited dielectric layers that separate upper-level interconnect lines from each other [T1].

The M2 module receives the planarized copper-and-dielectric surface produced by M1 polishing. Its own initial dielectric cap deposition protects that surface before the next dielectric stack is built. M2 then provides another wiring level connected to the underlying conductors through vias. In the broader 28nm Planar metal-one interconnect integration process flow context, M2 acts as the first scaled-pitch interconnect layer, demanding stringent lithographic control and dielectric integration.

Downstream, the M2 module delivers a planarized, electrically isolated, and mechanically stable surface for the 28nm Planar upper-metal interconnect integration modules to build upon. The quality of the M2 surface — its planarity, dielectric integrity, and via-to-line alignment — directly impacts the performance and reliability of every subsequent metal layer. Thus, M2 combines tight pitch patterning, low-k dielectric integration, and dual-damascene copper fill into a single cohesive module.

Entry State and Sequence Logic

Upstream Dependencies

M1 chemical mechanical polishing leaves exposed copper regions embedded in dielectric. Residue, native surface oxidation, and organic contamination can affect adhesion of the cap subsequently deposited at the start of M2. The relevant incoming interface is therefore the polished copper-and-dielectric surface, not a previously completed cap layer.

Surface preparation before cap deposition addresses residues and the chemical state of exposed copper. The following capping layer must adhere to both copper and neighboring dielectric while presenting a compatible surface for subsequent TEOS oxide and low-k growth. The quality of this interface affects both diffusion blocking and mechanical integrity.

M2 NDC Deposition Integration Principles

Nitrogen-doped carbon (NDC) films are formed through plasma- or thermally activated reactions that decompose carbon-containing precursors in the presence of nitrogen species, creating a covalently bonded amorphous network containing C–C, C–N, and limited C–H bonds. The incorporation of nitrogen modifies the electronic structure and bonding configuration of the carbon matrix, forming a dense, chemically inert barrier that suppresses copper out-diffusion into overlying low-k dielectrics. This NDC layer acts as a copper diffusion barrier and etch stop, establishing a chemically compatible and mechanically stable interface for the subsequent TEOS oxide buffer deposition.

Dielectric cap design balances barrier integrity, mechanical behavior, and parasitic capacitance. A denser, nitrogen-rich film provides effective kinetic blocking against copper atomic migration by raising the diffusion activation energy, but it introduces a higher dielectric constant compared to softer bulk dielectrics. This trade-off between diffusion barrier capability and interline capacitance management is a key integration consideration in the M2 dielectric stack.

Physical and Chemical Mechanisms

Low-k Dielectric Deposition

Following the deposition of the NDC cap and the intermediate TEOS oxide buffer layer, the bulk SiCOH low-k dielectric is grown. Low dielectric constant (low-k) materials as an interlayer dielectric (ILD) with copper interconnects display [P2] significant operational advantages in reducing RC propagation delays. SiCOH modifies the silicon dioxide matrix by replacing a portion of Si–O bonds with organic Si–CH3 methyl groups. These methyl groups occupy physical volume and lower the polarizability of the dielectric network, reducing the relative dielectric constant below that of conventional SiO2. Lowering the dielectric constant minimizes interline capacitance between closely spaced M2 copper lines, directly suppressing RC signal propagation delay.

During PECVD, organosilane precursors are fragmented in an RF plasma, producing reactive species that condense onto the substrate to form a SiCOH network. Tuning the precursor flow ratio, RF power, and substrate temperature determines the carbon concentration, network density, and mechanical modulus. While higher carbon incorporation lowers the dielectric constant, it simultaneously reduces mechanical strength and increases sensitivity to plasma oxidation during patterning.

Dual-Damascene Patterning

The patterning sequence in this 28nm planar module employs a trench-first metal hard mask (TFMHM) integration scheme. In this architecture, the metal-two trench pattern is photolithographically defined and etched into an overlying metal hard mask stack first, followed by planarization, via lithography, and dual-damascene dielectric etching. A spin-on organic material fills the open trench hard mask windows and planarizes the surface before via lithography patterns the via holes. Subsequent plasma etching transfers the via through the low-k dielectric stack down to the cap layer, followed by etching the trench pattern into the upper bulk dielectric.

Fluorine-based plasma chemistries (such as fluorocarbons mixed with carrier gases) are used to etch SiCOH, converting silicon into volatile SiF4 species while removing carbon as CO and CO2 byproducts. Achieving high selectivity against underlying hard masks and the NDC etch stop requires precise control of ion bombardment directionality and polymer passivation on sidewalls. Insufficient ion directionality leads to bowed via sidewalls, increasing parasitic capacitance and complicating barrier deposition, whereas excessive physical sputtering can erode the NDC cap and damage underlying M1 lines.

Copper Barrier, Seed, and Fill

Following dual-damascene etching, the opened trenches and vias are lined with a refractory diffusion barrier stack — typically tantalum nitride/tantalum (TaN/Ta) — deposited via physical vapor deposition (PVD). The TaN/Ta barrier prevents copper atoms from migrating into the low-k SiCOH dielectric, preventing field-assisted leakage. A thin, continuous copper seed layer is then sputtered on top of the barrier to provide an electrical conduction layer for plating.

Copper gap fill is performed using electrochemical plating (ECP) with organic bath additives (accelerators, suppressors, and levelers). Superconformal "bottom-up" filling is driven by the preferential accumulation of accelerator additives at the bottom of narrow vias and trenches, enhancing localized copper deposition rates relative to the field regions. This mechanism prevents the formation of central seams or keyhole voids, ensuring low line resistance and high electromigration immunity.

CMP Planarization

Chemical mechanical planarization (CMP) has become one of the most critical processes in semiconductor device fabrication to achieve global planarization [P5]. In the M2 module, CMP removes the excess copper overburden and TaN/Ta barrier layer from field regions, isolating individual copper lines and vias within the SiCOH dielectric matrix. The CMP process combines chemical oxidation and complexation in the slurry with mechanical abrasion by pad asperities and sub-micron abrasive particles.

Pattern density and feature width influence local polishing behavior. Dense patterned regions can experience erosion of the metal-and-dielectric surface, while wide copper features are susceptible to dishing below the surrounding dielectric. Layout density management, including dummy fill where appropriate, can reduce variation, but does not guarantee a perfectly uniform final surface.

Interfaces and Failure Propagation

Polished M1 Surface to M2 Cap Interface

The interface between the polished M1 copper/dielectric surface and the newly deposited M2 NDC cap is a critical structural boundary. Contamination, oxidation, or weak bonding can contribute to delamination under thermal or mechanical stress. Defects at this boundary can compromise later interconnect resistance and reliability.

SiCOH to Etch Stop Interface

During via etching, the plasma process must stop reliably on the M2 NDC layer without punching through into the M1 copper line underneath. Insufficient etch selectivity can erode the NDC cap, exposing M1 copper to plasma ambient and causing copper sputtering or oxidation, which increases via contact resistance. Conversely, incomplete NDC clear during the final via open step leaves dielectric residues at the bottom of the via, severely degrading electrical contact integrity.

Low-k Dielectric Plasma Damage

During dual-damascene etch and photoresist strip steps, reactive oxygen or fluorine radicals in the plasma extract methyl (–CH3) groups from the SiCOH sidewalls, leaving behind dangling bonds that readily absorb moisture upon atmosphere exposure. The absorption of water and incorporation of hydrophilic OH groups cause a significant increase in dielectric constant due to the high polarizability of the OH groups. This localized damage shell along trench sidewalls increases interline capacitance and leakage currents, degrading overall BEOL performance.

Electromigration and Stress Migration

Under high current density operating conditions, momentum transfer from flowing conduction electrons drives directional transport of copper atoms along grain boundaries and interfaces — a phenomenon known as electromigration. Because the upper copper/NDC cap interface is often the dominant fast-diffusion pathway, strong interfacial adhesion between copper and the cap layer is essential to suppress void nucleation and extend device operating life. Additionally, thermal expansion mismatch between copper and the flexible low-k SiCOH matrix generates mechanical stress gradients, which can induce stress migration voiding inside narrow vias.

Edge Placement Error and Overlay

As interconnect dimensions scale, edge placement error (EPE) — driven by optical lithography overlay offsets and critical dimension (CD) variations — narrows the process window. Misalignment of Via1 relative to the underlying M1 line or overlying M2 trench can reduce the contact area, raising via resistance, or cause electrical leakage to adjacent un-connected features. Tight overlay budgets, calibrated optical proximity correction (OPC), and rigorous design rules are necessary to preserve yield.

Walk the Real Module

For engineers and students seeking to trace the step-by-step physical implementation of the 28nm Planar M2 interconnect module, an interactive flow sequence is available. You can Open M2 Step 205 in the interactive flow to examine the detailed manufacturing sequence, from initial NDC cap deposition through low-k deposition, dual-damascene lithography and etch, metal barrier/seed sputtering, copper ECP, and final CMP.

The sequence illustrates why the surface condition established by cleaning must be preserved until the subsequent layer is deposited. Close integration of compatible operations can reduce recontamination, but a particular shared-vacuum arrangement is not a universal requirement established by this educational flow.

Related Learning Paths

To build a holistic understanding of 28nm Planar BEOL architecture, explore these adjacent module guides:

• The 28nm Planar metal-one interconnect integration process flow article details the baseline M1 module, establishing the initial copper interconnect level and capping dielectric upon which M2 is constructed.
• The 28nm Planar upper-metal interconnect integration process flow article covers M3 and thicker upper metal layers, where pitches relax and the integration focus shifts to power distribution and pad robustness.
• The comprehensive 28nm Planar process flow article provides the full manufacturing overview, linking FEOL transistor formation, contact plugs, and multi-level BEOL interconnect modules into a unified sequence.

Together, these resources form a complete educational framework spanning local contacts, fine-pitch low-k interconnects, and global power distribution.

Future Outlook

While the 28nm planar node remains widely produced, the low-k dielectric and barrier integration concepts established at M2 continue to inform scaled interconnect engineering. Managing dielectric damage, interfacial barrier strength, and CMP variation remains fundamental as interconnect pitches contract. Further scaling introduces extreme low-k formulations and modified barrier stacks to meet latency and reliability demands.