28nm Planar Metal-Two Interconnect Integration: Process Flow Principles and Mechanism Deep Dive

Role in the Complete Flow

The 28nm Planar metal-two (M2) interconnect integration module occupies a pivotal position in the back-end-of-line (BEOL) sequence of a 28nm planar CMOS process [P1]. By the time the wafer enters the M2 module, the front-end-of-line (FEOL) transistor structures — including high-k/metal gate (HKMG) or poly-SiON gate stacks depending on the flavor of the 28nm platform — have been fully formed, and the contact module has established the first electrical bridge between the silicon channel and the interconnect stack [P4]. The 28nm Planar process flow has already produced the metal-one (M1) layer, which routes the lowest level of signal and power interconnects above the contact plugs [P1].

What the M2 module receives, therefore, is a planarized surface capped by the M1 metal lines and their overlying dielectric cap [A2]. The M2 module's responsibility is to build the second level of copper interconnects on top of M1, connecting M1 lines to each other and to higher metal layers through via structures, while introducing the first significant deployment of low-k dielectric materials in many 28nm BEOL stacks [P1]. In the broader 28nm metal-two interconnect integration context, M2 acts as the first "scaled pitch" interconnect layer — meaning it typically operates at a tighter pitch than M1, demanding more stringent lithographic control and more aggressive dielectric engineering [P1].

Downstream, the M2 module must deliver a planarized, electrically isolated, and mechanically robust surface that the 28nm Planar upper-metal interconnect integration modules can build upon [P1]. The quality of the M2 surface — its planarity, dielectric integrity, and via-to-line alignment — directly constrains the performance and reliability of every subsequent metal layer [P1]. In this sense, M2 is not merely "another metal level"; it is the first layer where the interconnect scaling challenge of 28nm becomes fully manifest, combining tight pitch, low-k dielectric integration, and dual-damascene copper fill into a single cohesive module [T2].

Entry State and Sequence Logic

Upstream Dependencies

The M2 module process flow begins after the M1 module has completed its chemical mechanical polishing (CMP) step, leaving a globally planarized copper surface with a dielectric cap that serves as both a chemical barrier and an etch stop for subsequent patterning [P4]. The integrity of this cap is essential: any residual copper residue or cap delamination from the M1 module will propagate upward into the M2 dielectric stack, creating resistive shorts or adhesion failures [T1].

Prior to M2 dielectric deposition, the wafer surface must be thoroughly cleaned to remove particulates and native oxide regrowth on exposed M1 copper [T1]. This cleaning step establishes the baseline for the M2 NDC (nitride-dielectric cap) deposition that follows [P4]. The M2 NDC deposition integration principles dictate that the cap layer must adhere well to both the underlying copper and the overlying low-k dielectric, creating a trilayer interface system whose mechanical and chemical compatibility determines the reliability of the entire M2 stack [P1].

M2 NDC Deposition Integration Principles

The M2 NDC layer serves multiple functions simultaneously: it acts as a copper diffusion barrier, an etch stop for via patterning, and a mechanical interface between the harder M1 cap and the softer low-k dielectric above [P1]. The deposition of M2 NDC must achieve conformal coverage over the topography left by M1 patterning and CMP, which requires careful control of the precursor chemistries and deposition parameters [P4]. The integration logic here is that any pinhole or discontinuity in the NDC layer creates a direct copper diffusion pathway into the low-k dielectric, which would degrade dielectric integrity and increase leakage [A1].

The choice of NDC material at the 28nm node reflects a trade-off between diffusion barrier effectiveness and dielectric constant [P1]. A denser, more silicon-rich nitride provides superior barrier performance but introduces higher parasitic capacitance between M1 and M2 [P1]. Conversely, a more carbon-rich or oxygen-rich NDC reduces capacitance but may compromise barrier quality [P1]. This trade-off is a defining feature of M2 module integration at 28nm, and it must be resolved before proceeding to the low-k dielectric deposition [P1].

Physical and Chemical Mechanisms

Low-k Dielectric Deposition

The primary dielectric material used in the M2 module at 28nm is typically a carbon-doped oxide, often referred to as SiCOH, deposited by plasma-enhanced chemical vapor deposition (PECVD) [P1]. SiCOH is fundamentally a silicon dioxide network in which some Si–O bonds are replaced by Si–CH₃ bonds, introducing organic methyl groups that lower the material's polarizability and thus its dielectric constant [T2]. The physical mechanism is straightforward: the methyl groups occupy volume that would otherwise be filled by more polarizable Si–O–Si linkages, reducing the density of electric dipoles that respond to an applied field [T1]. This directly lowers the interline capacitance between adjacent M2 copper lines, which is the dominant component of RC delay at scaled pitches [P1].

The deposition chemistry involves organosilane precursors fragmented in a plasma environment, producing reactive radicals that condense on the wafer surface to form the SiCOH network [P2]. The ratio of silicon-containing fragments to organic fragments, the plasma excitation state, and the substrate thermal conditions collectively determine the carbon content, porosity, and mechanical modulus of the deposited film [T2]. Higher carbon content and higher porosity both lower the effective dielectric constant, but they also reduce the film's resistance to plasma damage during subsequent etch and strip steps — a trade-off that pervades the entire M2 module process flow [P1].

Dual-Damascene Patterning

The M2 interconnect is formed using a dual-damascene architecture, in which both the via holes (connecting downward to M1) and the trenches (forming the M2 lines themselves) are patterned into the SiCOH dielectric before a single copper fill [P1]. The patterning sequence can follow either a "via-first" or "trench-first" approach, but the 28nm planar flow typically employs a via-first scheme because it simplifies the etch stop integration and reduces the risk of trench-bottom etch non-uniformity [T1].

The etch chemistry for SiCOH relies on fluorine-based plasmas, which form volatile silicon fluoride byproducts and simultaneously remove carbon as COₓ species [P2]. The challenge is that the low-k dielectric is chemically similar to the hard mask and etch stop layers used to define the pattern, so achieving high selectivity requires careful plasma chemistry design [P2]. Ion bombardment directionality, controlled by the electrical biasing applied during etching, determines the verticality of the via and trench sidewalls [P2]. Insufficient directionality produces bowed profiles that increase parasitic capacitance and compromise copper fill; excessive directionality can erode the underlying M1 cap, creating via-to-M1 short circuits [P2].

Copper Barrier, Seed, and Fill

After patterning, the M2 trenches and vias must be lined with a diffusion barrier — typically a tantalum-based nitride — followed by a copper seed layer deposited by physical vapor deposition (PVD) [P1]. The barrier prevents copper from diffusing into the SiCOH low-k dielectric, which would cause dielectric leakage and potentially catastrophic interlevel shorting [T1]. The seed layer provides the conductive surface necessary for the subsequent electrochemical plating (ECP) of copper to fill the features [T1].

The fill mechanism in ECP relies on the superconformal deposition of copper into narrow trenches and vias, driven by the presence of organic additives in the plating bath that differentially suppress deposition on flat surfaces relative to recessed features [P4]. This differential suppression — controlled by the interplay of accelerator, suppressor, and leveler additives — enables bottom-up filling that avoids voids or seams in the center of the feature [P4]. Any void in the M2 copper fill creates a localized charge concentration point that accelerates electromigration failure, so the quality of the plating chemistry and the geometry of the pre-plated profile are both critical [P1].

CMP Planarization

The final step in the M2 module is copper CMP, which removes the excess copper overburden and the barrier layer from the field regions, leaving copper only within the patterned trenches and vias [P4]. The physical mechanism of CMP combines chemical softening of the surface — through oxidation and complexation reactions in the slurry — with mechanical abrasion by polishing pad and slurry particles [P4]. The removal behavior depends on local mechanical force, which is in turn governed by the local pattern density: high-density regions experience accelerated erosion, while low-density regions are susceptible to dishing [P4].

To manage this pattern dependence, the 28nm platform employs coverage design rules and dummy fill insertion strategies [P4]. Dummy metal structures are placed in sparse layout regions to equalize local pattern density, ensuring that the M2 surface after CMP is sufficiently planar for the subsequent M3 lithography [P4]. Without adequate dummy fill, dishing in low-density areas would create depth-of-focus challenges for the M3 exposure, while erosion in high-density areas would thin the M2 lines and increase their resistance [P4].

Interfaces and Failure Propagation

M1 Cap to M2 NDC Interface

The interface between the M1 dielectric cap and the M2 NDC layer is the first critical boundary in the M2 stack [P1]. If the M1 cap surface is not clean or if the M2 NDC deposition produces poor adhesion, delamination can occur during subsequent thermal cycles or CMP [P4]. Delamination at this interface manifests as elevated via resistance or, in severe cases, complete open circuits in the M1-to-M2 path [T1]. The direction of failure propagation is upward: a defective M1 cap surface degrades the M2 NDC, which in turn degrades the SiCOH adhesion, ultimately compromising the entire M2 stack [T1].

SiCOH to Etch Stop Interface

The interface between the SiCOH low-k dielectric and the NDC etch stop layer is another failure-prone boundary [P2]. During the via-first etch, the plasma must stop precisely at the NDC surface without penetrating through to the M1 copper [P2]. If the etch selectivity is insufficient — meaning the etch chemistry attacks the NDC too aggressively — the NDC becomes thinned or breached, exposing M1 copper to the via pre-clean step [P3]. This exposure can cause copper sputtering or oxidation, both of which increase via contact resistance [P4]. Conversely, if the selectivity is too high in favor of the NDC, the via profile may develop a "foot" at the bottom, reducing the effective via cross-section and increasing localized electrical stress, which accelerates electromigration [P1][P3].

Low-k Dielectric Plasma Damage

One of the most insidious failure modes in the M2 module is plasma damage to the SiCOH low-k dielectric [P2]. During the dual-damascene etch and the subsequent photoresist strip, the plasma can break Si–CH₃ bonds in the SiCOH, replacing them with Si–OH or Si–F bonds [P2]. This chemical modification increases the dielectric constant of the damaged layer — sometimes approaching that of undoped SiO₂ — and creates a hydrophilic surface that absorbs moisture, further degrading insulating capability [T2]. The damage is concentrated in a thin shell along the trench sidewalls and via sidewalls, but its cumulative effect on interline capacitance and leakage can be significant (Engineering Practice). Because the damaged layer is thin and buried under the copper/barrier stack, it is difficult to detect by inline metrology and often only manifests as yield loss in final electrical test [P1].

Electromigration and Stress Migration

The M2 copper lines, particularly those carrying high charge carrier fluxes, are subject to electromigration — the gradual drift of copper atoms along the direction of electron flow, driven by momentum transfer from conduction carriers to lattice atoms [T1]. The M2 NDC cap layer plays a crucial role in electromigration reliability because the copper-dielectric interface at the top of the M2 line is typically the fastest diffusion path [P1]. A well-integrated NDC layer with strong adhesion to copper can pin this interface and extend electromigration lifetime [P1]. Conversely, a poorly deposited or plasma-damaged NDC creates a weak interface that accelerates void formation and line open-circuit failure [P1].

Stress migration — driven by thermal expansion mismatch between copper and the surrounding dielectric — can also cause voiding in M2 lines, particularly in wide lines where the copper is less constrained [T1]. The lower mechanical modulus of SiCOH compared to SiO₂ means the dielectric provides less mechanical confinement, making stress-induced voiding more likely than in older technology nodes that used denser dielectrics [P1].

Edge Placement Error and Overlay

The M2 module is also sensitive to edge placement error (EPE), which arises from the combination of lithographic overlay error and critical dimension (CD) variation [P3]. EPE directly determines the minimum achievable metal spacing and, at 28nm pitches, can cause via-to-line shorting if the via is misaligned relative to the M2 trench edge [P3]. The relationship between minimum pitch and EPE follows a proportionality: tighter pitches demand lower EPE, and any increase in overlay or CD variation narrows the process window [P3]. In the M2 module, EPE is controlled through a combination of advanced lithographic correction, etch bias tuning, and design rule constraints on via-to-line spacing [P3].

Walk the Real Module

For engineers and students who want to trace the actual step-by-step sequence of the 28nm Planar M2 interconnect integration, an interactive flow is available that walks through each process step in order, from the initial M1 surface preparation through the final M2 CMP and inspection [P1]. You can Open M2 Step 205 in the interactive flow to explore the detailed module sequence and understand how each step contributes to the final M2 interconnect structure [P1].

The interactive flow is particularly valuable for understanding the ordering logic of the M2 module — why the NDC deposition must precede the SiCOH deposition, why the via etch must precede the trench etch in a via-first scheme, and why the barrier and seed deposition must occur in the same integrated vacuum environment as the pre-clean to avoid copper oxidation [P4]. By walking through each step, the reader can build a mental model of the causal chain that connects each process operation to the final electrical and reliability performance of the M2 interconnect layer [P1].

Related Learning Paths

To build a comprehensive understanding of the 28nm planar BEOL, readers should explore the adjacent modules in the interconnect stack:

• The 28nm Planar metal-one interconnect integration process flow article covers the foundational M1 module, which establishes the first copper interconnect layer above the contact plugs and defines the surface upon which M2 is built [P1]. Understanding M1 is essential because the M2 module inherits all of M1's topography and interface quality (Engineering Practice).
• The 28nm Planar upper-metal interconnect integration process flow article extends the discussion to M3 and beyond, where pitches relax, dielectric stacks become thicker, and the emphasis shifts from tight-pitch patterning to low-resistance power routing and packaging compatibility [P1].
• The overarching 28nm Planar process flow article provides the end-to-end integration perspective, showing how FEOL transistor formation, contact module, and BEOL interconnect modules fit together into a single cohesive manufacturing sequence [P1].

Together, these articles form a layered knowledge structure: the process flow article gives the top-down view, M1 explains the first interconnect layer, M2 (this article) explains the first scaled-pitch low-k interconnect layer, and the upper-metal article explains the transition to relaxed-pitch power and signal routing [P1].

Future Outlook

While the 28nm planar node remains a workhorse technology in high-volume manufacturing, the integration principles established in its M2 module continue to influence more advanced nodes [P1]. The trade-offs between dielectric constant, mechanical modulus, and plasma damage resistance that define SiCOH low-k integration at 28nm persist — and intensify — at 20nm, 16nm, and beyond [P1]. The introduction of ultra-low-k (ULK) porous dielectrics at more advanced nodes pushes the mechanical integrity challenge even further, requiring innovations in dielectric composition, pore sealing, and mechanical buffer layers [P1].

Looking forward, the industry is also exploring backside power delivery architectures that could fundamentally reshape the BEOL interconnect stack [A1]. By moving power routing to the wafer backside, these architectures could reduce the electrical load burden on frontside metal layers like M2, potentially relaxing electromigration constraints and enabling further pitch scaling [A1]. However, such architectures introduce their own integration challenges, including high-aspect-ratio through-silicon via formation and wafer bonding alignment, which are active areas of research and development [T2].

Finally, the emergence of new dielectric materials — including metal-organic frameworks, air-gap structures, and self-assembling porous films — represents a frontier in low-k dielectric engineering [A2]. These materials aim to push the effective dielectric constant below what SiCOH can achieve, but their integration into dual-damascene process flows at production scale remains a significant engineering challenge [T2]. The M2 module at 28nm, with its well-characterized SiCOH and NDC stack, serves as a reference architecture against which these future innovations can be benchmarked [P1][T2].