28nm Planar Upper-Metal Interconnect Integration: Process Flow Principles and Integration Logic

Role in the Complete Flow

The 28nm Planar upper-metal interconnect integration represents a critical transition zone in the back-end-of-line (BEOL) process stack, where the interconnect hierarchy shifts from tightly pitched lower-metal signal routing to progressively wider and thicker upper-metal layers designed for power distribution and global signal delivery. At this technology node, the upper-metal module receives a partially completed BEOL stack from the preceding metal levels — typically including lower copper interconnect layers embedded in ultra-low-k (ULK) or low-k dielectric matrices — and must deliver a robust, planarized, and electrically reliable interconnect tier that can serve as the foundation for subsequent redistribution and pad structures.

The fundamental role of this module is twofold. First, it must provide signal routing continuity with acceptably low resistance and capacitance, ensuring that RC delay does not become the dominant bottleneck as transistor performance improvements from front-end scaling are not negated by interconnect parasitics. Second, it must establish a mechanically stable dielectric–metal architecture that can withstand downstream processing — including additional metal layer deposition, chemical mechanical polishing (CMP), and thermal treatments — without introducing reliability hazards such as copper diffusion, dielectric cracking, or electromigration-induced voiding.

In the 28nm Planar process flow, the upper-metal interconnect integration is where the cumulative effects of pattern density, CMP planarization uniformity, and dielectric integrity converge. The module must deliver a surface that is sufficiently planar for subsequent lithographic patterning, because any residual topography propagates forward and degrades focus uniformity in downstream optical exposure steps. Furthermore, the Cu barrier integrity established here directly governs long-term electromigration lifetime, since copper diffuses rapidly through dielectrics if the barrier is compromised.

Entry State and Sequence Logic

Upstream Dependencies

The 28nm upper-metal interconnect integration enters the process flow after the completion of one or more lower-metal damascene levels. The incoming wafer state includes patterned copper lines and vias embedded in a dielectric stack, with the topmost surface having undergone CMP planarization. The quality of this incoming surface — its planarity, residual copper thickness, barrier residue, and dielectric damage profile — sets the initial conditions for everything that follows in the upper-metal module.

A critical upstream dependency is the condition of the dielectric surface after CMP. Chemical mechanical polishing removes the overburden copper and barrier material, but it can also introduce surface defects such as erosion in high-pattern-density regions and dishing in wide metal features. These topographic non-uniformities must be understood as inputs, not merely as local phenomena, because they influence subsequent dielectric deposition conformality and lithographic focus budgets at the next level.

Sequence Positioning and Module Ordering

Within the broader 28nm Planar process flow, the upper-metal interconnect integration sits between the lower-metal damascene modules and the redistribution/pad modules. This positioning is deliberate: the upper-metal layers serve as a bridge between the fine-pitched signal interconnects below and the coarse-pitched power and pad structures above. The sequence logic dictates that each metal level must be fully completed — dielectric deposition, lithography, etch, barrier/seed deposition, copper electroplating, and CMP — before the next level begins, because the subsequent level's patterning fidelity depends on the planarity delivered by the prior level's CMP.

The M3_PLUS module process flow specifically addresses this transitional tier, where the integration logic must reconcile the competing demands of finer-pitched routing below with the wider structures above. The module's position in the sequence means that any defects or non-uniformities introduced here propagate downward into reliability failures and upward into patterning yield loss.

Physical and Chemical Mechanisms

Dielectric Deposition and the Role of Nitrogen-Doped Carbide

A cornerstone of the 28nm upper-metal interconnect integration is the deposition of the intermetal dielectric (IMD) stack, which includes nitrogen-doped carbide (NDC) as a critical etch-stop and barrier layer. T8M3 NDC Deposition serves as a key step in this stack, providing a dielectric film that simultaneously acts as a copper diffusion barrier, an etch-stop for trench and via patterning, and an adhesion promoter between the ULK dielectric and the metallic cap.

The integration principles behind T8M3 NDC Deposition stem from the material's dual functionality. Nitrogen-doped carbide films are deposited through plasma-enhanced chemical vapor deposition (PECVD), where precursor fragmentation and film densification are governed by the plasma energy and substrate conditions. The nitrogen incorporation modifies the carbon-rich matrix, increasing its density and improving its effectiveness as a Cu barrier — copper diffusion through the dielectric is a thermally activated process, and a denser, nitrogen-rich film raises the effective activation energy for diffusion, thereby suppressing copper migration into adjacent dielectric layers. The dielectric constant of NDC is higher than that of the surrounding ULK material, which creates a deliberate tradeoff: a thicker NDC layer improves barrier reliability but increases parasitic capacitance, while a thinner layer reduces capacitance but may compromise diffusion resistance. This parameter interaction direction — barrier integrity versus capacitance penalty — is a central design tension in the 28nm upper-metal interconnect integration.

Dual-Damascene Patterning and Trench Formation

The dual-damascene process is the foundational architecture for copper interconnect formation at 28nm. In this approach, both via and trench patterns are etched into the dielectric stack before a single metallization fill, eliminating the need for a separate metal etch step — a critical advantage given that copper is notoriously difficult to dry-etch. The physical mechanism involves sequential lithographic exposure and plasma etch steps that define the via openings first (or trenches first, depending on the integration scheme), followed by the complementary features.

The etch chemistry relies on fluorocarbon-based plasmas for dielectric etching, where the etch selectivity between the ULK dielectric and the NDC etch-stop layer is governed by the polymer-forming tendency of the etch gas. When the plasma reaches the NDC etch stop, the nitrogen-rich surface forms a less volatile byproduct layer that suppresses further etching, providing high chemical selectivity for depth control while still requiring careful timing to prevent over-etch into underlying metal. This etch-stop behavior is essential for maintaining via landing accuracy across pattern-density variations.

Copper Electroplating and Superfilling

After barrier and seed layer deposition — typically a tantalum-based Cu barrier followed by a copper seed layer — the trenches and vias are filled by electrochemical deposition (ECD). The superfilling mechanism is central to void-free metallization: organic additives in the plating bath (accelerators, suppressors, and levelers) adsorb differentially on the feature surfaces, accelerating deposition at the bottom of trenches relative to the top. This bottom-up filling behavior is governed by the competitive adsorption kinetics of the additives and the local current density distribution, which is in turn influenced by the feature geometry and the seed layer uniformity.

The Mayadas–Shatzkes model describes how resistivity increases as linewidth shrinks, because grain-boundary scattering becomes dominant when the grain size approaches the electron mean free path. At 28nm, while upper-metal lines are wider than the lowest levels, the resistivity–dimension relationship still matters for the narrower upper-metal features, and the grain structure established during plating and subsequent anneal directly affects both resistance and electromigration resistance.

CMP Planarization Chemistry

The final step in each damascene level is CMP, which removes the copper overburden and barrier material, leaving metal only in the trenches and vias. In copper interconnect processing, a two-step chemical mechanical polishing sequence is conventionally used where the first step removes the bulk Cu layers and the second step removes the barrier layer, hard/soft masks and the dielectric film [P4]. The mechanism couples chemical and mechanical action: the slurry chemically oxidizes or complexes the copper surface, forming a softer passivation layer that is then mechanically abraded by the polishing pad and abrasive particles.

Polishing behavior in metal chemical mechanical planarization depends strongly on pattern uniformity across the wafer surface because the CMP process acts simultaneously on all the materials exposed, each of which necessarily have a different local CMP rate [P3]. Uneven distribution of device structures across the layout can cause dishing of metal lines and erosion of dielectrics of a layer during planarization, which can result in critical or killer defects in chips [P5]. High-density regions experience greater pad pressure and faster removal, while isolated wide features are susceptible to dishing. For the 28nm upper-metal interconnect integration, CMP planarization quality directly determines the surface topography that the next lithographic step must accommodate.

Interfaces and Failure Propagation

Barrier–Dielectric Interface

The interface between the Cu barrier and the surrounding dielectric is the first line of defense against copper diffusion. In the 28nm upper-metal interconnect integration, the barrier must be continuous and conformal, particularly at the bottom corners of trenches and along via sidewalls where coverage is challenged by the feature geometry. A discontinuous or thinned barrier allows copper to diffuse into the dielectric under thermal stress, leading to leakage current increases and potential dielectric breakdown.

The directional tradeoff here is clear: scaling the barrier thinner reduces the effective cross-sectional area occupied by non-copper material, improving the copper volume fraction and lowering line resistance, but it increases the risk of barrier discontinuity. This is particularly acute at the upper-metal levels where wider trenches may tempt relaxed barrier control, yet the longer current-carrying paths and higher current densities make barrier integrity equally critical.

NDC–ULK Interface and Delamination Risk

The T8M3 NDC Deposition creates an interface between the nitrogen-doped carbide etch-stop/barrier and the ULK dielectric. This interface is mechanically vulnerable because NDC is a denser, higher-modulus material while the ULK is intentionally porous and mechanically weak. The adhesion between these layers depends on the chemical bonding established during deposition — the nitrogen and carbon species in the NDC film must form bridging bonds with the ULK surface, and any plasma damage or surface contamination from upstream processing weakens this bond.

Delamination at this interface propagates as a yield-limiting failure: cracks initiate at the weak interface and can extend laterally, causing metal line opens or inter-level shorting. The propagation direction is typically from regions of high mechanical stress — such as wide metal areas where CMP dishing creates step height non-uniformity — toward the surrounding dielectric.

CMP-Induced Damage and Downstream Consequences

The CMP step that planarizes each metal level can introduce damage that propagates into subsequent processing. Copper erosion in dense-pattern regions reduces the effective metal height, increasing line resistance and creating resistance non-uniformity that affects timing closure. Dishing in wide metal areas creates local step heights that challenge the depth of focus for the next lithographic level, potentially causing patterning CD variation.

Furthermore, the ULK dielectric is susceptible to plasma damage during the CMP-related cleaning and the subsequent dielectric deposition steps. Plasma exposure can break Si–C and Si–O bonds in the ULK, creating a damaged surface layer with increased dielectric constant and moisture uptake. This damage degrades the capacitance reduction benefit that motivated the ULK material in the first place, and moisture trapped in the damaged layer can outgas during subsequent thermal processing, causing via voiding or adhesion failures.

Air Gap as a Mitigation Strategy

One advanced approach to managing the capacitance–reliability tradeoff is the introduction of air gaps in selected inter-metal spaces. By recessing the IMD after copper CMP and using a pinch-off mechanism during subsequent dielectric deposition, voids with the lowest possible dielectric constant (air) are selectively formed between metal lines. This approach can achieve capacitance reductions that would otherwise require increasingly porous — and mechanically weaker — ULK materials. However, the air gap process introduces its own interface challenges: the gap liner must hermetically seal the void to prevent moisture ingress, and the step height at the gap edges must be controlled to avoid CMP and lithography issues at the next level.

Walk the Real Module

To explore the actual step-by-step execution of the 28nm upper-metal interconnect integration, readers can Open M3_PLUS Step 225 in the interactive flow to trace the module in its full process context.

The upper-metal interconnect module process flow at 28nm begins with the arrival of a planarized surface from the preceding metal level. The sequence initiates with the deposition of the diffusion barrier and etch-stop layer via PECVD over the lower copper surface. This nitrogen-doped carbide layer then undergoes ultraviolet thermal curing to cross-link and densify the dielectric matrix. Next, plasma-enhanced oxide deposition forms the lower dielectric foundation, followed by an interleaved silicon nitride layer to enhance structural stability and etch selectivity, and a bulk dielectric oxide deposition to complete the intermetal dielectric stack.

Dual-damascene patterning begins with depositing a dielectric anti-reflective coating to control photolithographic reflections during via exposure. Photolithography defines the via patterns, after which anisotropic plasma etching cuts through the dielectric stack down to the etch stop. A post-etch wet chemical strip cleans away polymer residues and photoresist.

To prepare for trench patterning, a planarizing anti-reflective coating is applied to fill the via cavities and then recessed to set the via plug height. Photolithography subsequently defines the upper trench pattern, and plasma etching forms the trench in the bulk dielectric. The residual etch-stop liner at the bottom of the via is then selectively removed to expose the underlying copper contact.

Metallization proceeds with pre-clean surface treatment and wetting layer deposition, followed by conformal physical vapor deposition of a tantalum-based diffusion barrier bilayer and a continuous copper seed layer. Electrochemical copper plating fills the dual-damascene features using superfilling additives to prevent void formation. Finally, a two-step chemical mechanical polishing process removes excess copper overburden and barrier material, yielding a flat, planarized surface for subsequent integration.

For a broader understanding of how this module fits within the overall 28nm Planar metal-two interconnect integration process flow, the transition from lower-metal to upper-metal levels marks a shift in design priorities — from density-driven routing to performance-driven power delivery and signal integrity.

Interfaces with Adjacent Modules

The upper-metal interconnect integration does not exist in isolation; it is tightly coupled to both upstream and downstream modules. Downstream, the 28nm Planar redistribution via and aluminum pad integration process flow depends on the planarity and surface quality delivered by the upper-metal CMP. The redistribution layers and aluminum pad structures are significantly larger in dimension, and any residual topography from the upper-metal levels amplifies through the thicker dielectric films deposited above.

Upstream, the lower-metal interconnect modules deliver the signal routing that the upper-metal levels must collect and redistribute. The interface between these tiers — typically a via connection from the uppermost lower-metal layer to the lowermost upper-metal layer — is a reliability-critical junction where electromigration and stress migration failures often initiate. The Cu barrier continuity across this interface, and the alignment between the via and the underlying pad, are the key process control points.

Future Outlook

As the semiconductor industry pushes beyond 28nm, several trends are reshaping the upper-metal interconnect landscape. The adoption of air gap technology represents a shift from material-based low-k solutions to structural low-k solutions — leveraging the lowest possible dielectric constant (air) in selectively targeted regions. The timing-criticality-aware approach to air gap deployment demonstrates that performance gains depend not merely on the process capability but on the co-optimization of design and process: air gaps placed on timing-critical paths can deliver performance improvements, provided the routing topology supports gap formation.

Another emerging direction is the exploration of barrierless contact schemes using materials such as ruthenium, which combines low resistivity with inherent diffusion resistance, potentially eliminating the need for a separate Cu barrier layer at critical interfaces. While this approach has been demonstrated at the contact level, its extension to interconnect metallization could simplify the upper-metal integration by reducing the number of deposited layers and improving the copper volume fraction in narrow lines.

On the modeling front, machine-learning-based compact models for parasitic capacitance are emerging as essential tools for capturing the complex geometry–capacitance relationships at advanced nodes, where systematic process variations — linewidth drift, sidewall angle variation, dielectric thickness non-uniformity — interact combinatorially rather than independently. These models enable more accurate timing sign-off and help bridge the gap between design intent and silicon reality.

Finally, the backside power delivery architecture, where power rails are formed on the wafer backside and connected to frontside devices through power vias, represents a paradigm shift that could fundamentally alter the upper-metal interconnect role — transitioning signal and power routing to separate physical planes and potentially simplifying the frontside upper-metal integration.

Related Learning Paths

For engineers and students seeking to deepen their understanding of the 28nm Planar interconnect ecosystem, several adjacent topics provide complementary perspectives:

• The 28nm Planar process flow overview provides the full-module context in which the upper-metal interconnect integration operates, from front-end transistor formation through final passivation.
• The 28nm Planar metal-two interconnect integration process flow details the lower-metal damascene principles that establish the foundation upon which the upper-metal module builds.
• The 28nm Planar redistribution via and aluminum pad integration process flow covers the downstream modules that depend on the planarity and integrity delivered by the upper-metal interconnect integration.

Together, these articles form a continuous learning path from the first metal level through the final pad structure, with the upper-metal interconnect integration serving as the pivotal transition between fine-pitched signal routing and coarse-pitched power distribution.