28nm Planar Redistribution Via and Aluminum Pad Integration: Process Flow Principles and Integration Logic

Role in the Complete Flow

The 28nm Planar redistribution via and aluminum pad integration module occupies a critical position near the terminal portion of the back-end-of-line (BEOL) sequence [T2]. At this stage, the wafer has already passed through the complete copper interconnect stack — from the first metal level through the 28nm Planar upper-metal interconnect integration process flow — and the module's task is to bridge the final copper interconnect to externally accessible aluminum bonding pads [T1]. This bridging function is essential because the upper copper levels, while excellent for on-chip routing, are not suitable for direct wire bonding or solder bump attachment due to oxidation susceptibility and reliability concerns (Engineering Practice). The redistribution via (RV) serves as the vertical interconnect element that transfers electrical signals from the uppermost copper metal to the aluminum pad, while the RV nitride provides dielectric isolation and passivation around this transition region [P1].

What this module receives is a wafer with a completed upper-metal interconnect stack, including the final passivation dielectric on top of the last copper level [A1]. What it must deliver downstream is a set of electrically functional, mechanically robust aluminum pads that are accessible for subsequent packaging operations — whether wire bonding, flip-chip bumping, or probe contact [T1]. The downstream consumer of this module is the assembly and packaging flow, which depends on pad integrity, planarity, and electrical continuity to achieve acceptable assembly yield [A1]. In the broader context of the 28nm Planar process flow, this module represents one of the last wafer-level fabrication steps before singulation and packaging, making its reliability and quality directly impactful on final product yield [T2].

Entry State and Sequence Logic

The entry state for the RV_APL module process flow is defined by the completion of all upper-metal interconnect layers and their associated dielectric passivation [A1]. At this point, the wafer surface presents a planarized dielectric surface over the final copper metal level, with no exposed conductive regions until the redistribution via openings are created [A1]. The sequence logic follows a strict dependency chain: first, the RV nitride is deposited as a continuous dielectric film; second, via openings are patterned and etched through this nitride to expose the underlying copper; third, a barrier layer is deposited to prevent interdiffusion between copper and aluminum; fourth, the via is filled; and finally, the aluminum pad is deposited and patterned [T1][A1].

The integration dependencies are multidirectional (Engineering Practice). The RV nitride deposition must be compatible with the underlying copper — meaning the deposition thermal budget must not degrade the copper microstructure or cause interfacial adhesion failure [P1]. Simultaneously, the nitride must provide sufficient etch selectivity during via patterning so that the underlying copper is not damaged during the nitride opening etch [T1]. The barrier layer, typically a refractory metal or metal nitride, must adherently coat the via sidewalls and bottom to block copper-aluminum intermetallic formation, which is a well-known reliability hazard [A1]. The aluminum pad deposition must achieve adequate step coverage over the via topography and form a continuous, low-resistance contact to the via fill material [T1].

The sequence also depends on the upstream 28nm Planar copper bump integration process flow decisions — if the subsequent packaging uses copper bumps rather than wire bonding, the aluminum pad specifications and the RV architecture may differ accordingly, though the core module sequence remains structurally similar [T2]. The choice of pad metallurgy and via fill method creates a fork in integration strategy that propagates constraints both upward and downward through the flow [T1].

Physical and Chemical Mechanisms

RV Nitride Deposition

The RV nitride is deposited by plasma-enhanced chemical vapor deposition (PECVD), which dissociates silicon- and nitrogen-containing precursors in a radio frequency (RF) plasma to form hydrogenated amorphous silicon nitride (SiN) films [P1]. The fundamental mechanism involves the creation of reactive radicals and ions in the plasma volume, followed by their adsorption and surface reaction on the substrate to build the SiN network [P2]. The film's intrinsic stress — whether compressive or tensile — is governed by the balance between chemical bond structures, hydrogen content, and ion bombardment effects during deposition [P1]. In the context of 28nm Planar redistribution via and aluminum pad integration, the RV nitride must serve dual roles: it acts as a dielectric isolator preventing short circuits between the via and adjacent structures, and it functions as a passivation layer protecting the underlying copper from environmental degradation [T1].

The integration principles of RV Nitride Deposition center on achieving a film that simultaneously satisfies mechanical, chemical, and electrical requirements [P1]. Mechanically, the film must exhibit low residual stress to prevent delamination or cracking during subsequent thermal cycles [P1]. Chemically, the film must be dense enough to block moisture and ionic contaminants (Engineering Practice). Electrically, it must provide high breakdown strength and low leakage (Engineering Practice). The challenge, as demonstrated in related research, is that a single PECVD SiN film often cannot simultaneously satisfy all these requirements — necessitating careful optimization of plasma frequency, gas chemistry ratios, and potentially multilayer structural designs [P1]. Low-frequency and high-frequency or mixed-frequency deposition enables stress compensation between compressive- and tensile-stress layers, while the introduction of multilayer interfaces reduces overall residual stress via interfacial stress relaxation mechanisms [P1].

Barrier Layer and Via Formation

The barrier layer in the RV_APL module serves as a diffusion barrier between the copper interconnect and the aluminum pad [A1]. The physical mechanism relies on the barrier material's high thermodynamic barrier for interdiffusion — the refractory metal or metal nitride presents a dense, crystalline or amorphous structure that significantly slows the transport of copper atoms into aluminum and vice versa [T1]. Titanium nitride (TiN) is a common barrier choice because it provides adequate adhesion to both copper and aluminum, exhibits good conformal coverage in via geometries, and maintains thermal stability through downstream processing [T1].

Via formation follows a damascene-like approach: the RV nitride is patterned and etched to create openings that expose the underlying copper pad area [P1]. The etch mechanism is typically a plasma-based process where reactive species selectively remove the SiN while the underlying copper acts as an etch stop [P4]. The barrier layer is then deposited conformally over the via sidewalls and bottom, followed by via fill — which may use tungsten (W) plug deposition via chemical vapor deposition (CVD) or aluminum reflow, depending on the specific integration scheme [T1]. The W plug approach is favored because CVD deposition provides more conformal filling of the via hole compared to sputtered aluminum, producing a smoother topography over the via [T1].

Aluminum Pad Deposition

The aluminum pad is deposited as a thick metallic film over the barrier layer and surrounding RV nitride surface [P4]. The physical mechanism of aluminum pad formation involves sputter deposition or evaporative deposition, where aluminum atoms arrive at the substrate with sufficient kinetic momentum to form a continuous, adherent film [T1]. The pad must exhibit low contact resistance to the via, good adhesion to the surrounding dielectric, and sufficient mechanical robustness to withstand wire bonding thermocompression or thermosonic forces [A2]. The aluminum is typically alloyed with small amounts of copper and silicon to suppress electromigration and hillock formation during subsequent thermal exposures [T1].

Interfaces and Failure Propagation

RV Nitride / Copper Interface

The interface between the RV nitride and the underlying copper is a critical reliability node [P1]. If the SiN PECVD deposition conditions generate excessive compressive or tensile stress, the mismatch with the copper's mechanical properties can drive interfacial delamination — particularly during thermal cycling in downstream packaging [P1]. The directional tradeoff is clear: higher ion bombardment during PECVD increases film density and improves barrier properties but also increases compressive stress, raising delamination risk [P1]. Lower bombardment reduces stress but may compromise dielectric integrity [P1]. The failure propagates downstream as exposed copper regions corrode, leading to open circuits or elevated contact resistance at the via [T1].

Barrier Layer / Aluminum Interface

The barrier-aluminum interface must maintain stability through the final alloy thermal treatment and subsequent packaging thermal exposures [A1]. If the barrier layer is too thin or discontinuous, copper can diffuse through the barrier and form brittle copper-aluminum intermetallic compounds at the interface — these compounds are electrically resistive and mechanically fragile, leading to contact resistance increases and potential pad lift-off during wire bonding [T1][A1]. The propagation direction is from the via interface outward to the pad surface, where it manifests as bonding failures and elevated contact resistance [T1].

Aluminum Pad / RV Nitride Interface

The aluminum pad must adhere to the surrounding RV nitride surface to prevent pad lifting during mechanical stress from bonding operations [P4]. If the RV nitride surface is contaminated or if its surface energy is too low, the aluminum film may exhibit poor adhesion, leading to progressive pad detachment under thermal cycling [A1]. This failure mode propagates upward to the packaging interface, where detached pads cause electrical opens or intermittent connections [A1]. The passivation layer covering the metal sidewalls also suppresses lateral etching and undercut during subsequent processing, thereby enhancing structural stability [A1].

Dielectric Leakage and Integrity

The RV nitride must maintain its dielectric integrity throughout the module sequence [P1]. If the PECVD SiN film contains excessive hydrogen or exhibits poor density, it may develop leakage paths under electrical bias — particularly at the via sidewalls where electric fields concentrate [P1]. The failure propagates as a gradual increase in leakage, potentially leading to short circuits between adjacent vias or between the via and the underlying interconnect [P1]. The SiN PECVD process parameters that control hydrogen content — plasma excitation mode and gas chemistry ratios — directly influence this dielectric integrity, creating a coupling between deposition conditions and long-term device reliability [P1].

Walk the Real Module

To explore the detailed step-by-step execution of the 28nm Planar redistribution via and aluminum pad integration, readers can Open RV_APL Step 244 in the interactive flow [T2]. This interactive resource walks through the actual module sequence, showing how each step builds upon the previous one and how the integration dependencies are resolved in practice (Engineering Practice).

The module begins with the RV nitride deposition step, where SiN PECVD creates the dielectric foundation for the entire redistribution structure [P1]. Following this, the via pattern is defined lithographically and transferred into the nitride by plasma etch [T2]. The barrier layer is then deposited — covering the via sidewalls and bottom — after which the via is filled and any excess material is removed by a planarization or etchback technique [T1]. The aluminum pad is then deposited over the planarized surface, patterned to define the pad geometry, and the structure undergoes a final alloy thermal treatment to ensure ohmic contact and reduce interface charges [T1]."

Each step in this sequence carries integration implications: the nitride deposition thermal budget must be compatible with the underlying copper; the via etch must stop cleanly on copper without inducing damage; the barrier must be continuous and conformal; and the aluminum pad must achieve the required thickness and adhesion for downstream bonding [T1][A1]. The interactive flow link above provides a step-by-step visualization of how these requirements are met in the actual 28nm Planar process, allowing engineers to trace the causal chain from nitride deposition through final pad formation [P4].

Related Learning Paths

For engineers and students seeking to deepen their understanding of the 28nm Planar ecosystem, several adjacent topics provide complementary knowledge:

• The 28nm Planar upper-metal interconnect integration process flow covers the copper interconnect stack that feeds directly into the RV_APL module, providing essential context for the entry state and sequence dependencies that govern redistribution via formation [T2].
• The 28nm Planar copper bump integration process flow describes an alternative packaging path that may interface with or replace the aluminum pad approach, highlighting the tradeoffs between wire bonding and bump-based connectivity at the 28nm Planar node [T2].
• The overarching 28nm Planar process flow provides the top-level integration map, showing how the RV_APL module fits within the complete fabrication sequence from front-end-of-line through final passivation [T2].

Understanding these adjacent flows is essential for grasping the full integration logic of the 28nm Planar technology node, as each module's constraints and deliverables are defined by its neighbors in the process sequence [T1].

Future Outlook

The redistribution via and aluminum pad integration approach faces emerging challenges as semiconductor scaling continues [T2]. While the 28nm Planar node represents a mature technology, the principles established here — particularly around PECVD SiN stress engineering, barrier layer optimization, and copper-aluminum interface management — continue to inform more advanced nodes [P1][P4]."

One emerging direction is the adoption of plasma-enhanced atomic layer deposition (PEALD) for SiN films in redistribution applications [P4]. Atomic layer deposition (ALD) offers atomic-scale thickness control and superior conformality compared to conventional PECVD, which becomes increasingly important as via dimensions shrink and aspect ratios increase [P4][P2]. ALD's self-limiting surface reaction mechanism — where sequential precursor exposure builds the film layer by layer — enables precise thickness control that CVD-based techniques cannot achieve [P4]. However, the slower film growth inherent to ALD remains a throughput challenge for thick films such as those required for redistribution passivation [P2][P4].

Another trend is the exploration of spatial ALD under non-vacuum conditions with reduced thermal budgets, which attempts to combine the quality advantages of ALD with throughput approaching that of PECVD [P2]. Research in this area has demonstrated SiN deposition at significantly reduced thermal budgets, though challenges remain in achieving sufficient film purity — residual carbon and oxygen impurities can compromise dielectric performance [P2]. The spatial ALD approach separates precursor and co-reactant zones physically rather than temporally, enabling continuous substrate processing and higher throughput [P2].

For the aluminum pad itself, research continues into replacement metallurgies — including copper pads and nickel-palladium-gold stacks — that eliminate the need for a copper-aluminum barrier layer entirely, simplifying the module sequence and improving electromigration reliability [T1]. These approaches are gradually being adopted in advanced packaging flows, though the aluminum pad remains dominant in many 28nm Planar applications due to its proven wire bonding compatibility and cost effectiveness [P4]. The fundamental integration logic — dielectric isolation, via formation, barrier deposition, and pad metallization — will persist even as specific material choices evolve, making the principles discussed here transferable across technology generations [T1][P4].