28nm Planar Flow 28nm Process Step

NDC (SiCN) deposition establishes a physical barrier that prevents copper diffusion and ambient oxygen reaction .

Following the completion of the M2 copper Electrochemical Plating (ECP) and subsequent Chemical Mechanical Planarization (CMP) processes, the planarized copper and inter-level dielectric (ILD) surfaces are exposed to the ambient cleanroom environment, rendering the copper highly susceptible to rapid oxidation and corrosion . To prevent copper atoms and ions from rapidly di

ffusing into the surrounding dielectric under the influence of electric fields and thermal activation—which otherwise degrades the inter-metal dielectric isolation and leads to Time-Dependent Dielectric Breakdown (TDDB)—a robust capping barrier must be deposited . The T8M3 NDC (Nitrogen-Doped Carbide, or SiCN) Deposition step serves as this critical dielectric barrier and etch stop layer directly on top of the M2 Cu lines . This step acts as a physical barrier against copper out-diffusion and prevents ambient oxygen from reacting with the underlying copper (Engineering Practice). Crucially, the NDC layer also functions as a highly selective etch stop layer during the subsequent M3 dual-damascene via patterning processes (Engineering Practice), preparing the wafer for post-NDC UV curing and subsequent oxide/nitride bulk dielectric deposition steps .

The physical mechanism of NDC deposition utilizes Plasma-Enhanced Chemical Vapor Deposition (PECVD) to synthesize an amorphous hydrogenated silicon carbonitride ($a-SiC_xN_y:H$) film at temperatures compatible with the Back-End-of-Line (BEOL) thermal budget, typically restricted to below 400 °C to prevent copper recrystallization or voiding . During the PECVD process, volatile organosilane precursors (such as trimethylsilane or tetramethylsilane) are co-introduced with nitrogen and ammonia ($NH_3$) gases into the reactor chamber, where they are dissociated by radio-frequency (RF) energy into highly reactive silicon, carbon, and nitrogen radicals (Engineering Practice). These radicals adsorb onto the substrate surface and undergo a complex series of condensation and abstraction reactions, forming a dense, cross-linked amorphous network . The addition of nitrogen to the carbide network is critical as it passivates dangling bonds, decreases bulk leakage current by adjusting the density of electronic states , and establishes excellent chemical etch selectivity against silicon dioxide during subsequent reactive ion etching .

The selection of NDC (SiCN) over alternative dielectric barriers like stoichiometric silicon nitride ($Si_3N_4$) is dictated by the strict electrical performance requirements of advanced interconnect architectures . Although stoichiometric silicon nitride provides an excellent barrier to copper diffusion, its high dielectric constant ($k \approx 7.0$) severely increases the parasitic capacitance of the interconnect stack, leading to higher resistance-capacitance ($RC$) delay and power dissipation . NDC provides a lower dielectric constant ($k \approx 4.5 - 5.0$) while maintaining an equivalent or superior physical diffusion barrier capability to prevent copper migration . Unlike metallic barriers (such as TaN/Ta, Ru, or CoW alloys) that are selectively deposited inside trenches to facilitate direct contact , NDC must be a dielectric to prevent electrical shorting across the adjacent coplanar copper lines . The process window is tuned by adjusting the ratio of nitrogen-to-carbon precursors and the plasma density (Engineering Practice); increasing nitrogen flow rate improves film density and barrier performance but increases the $k$-value, requiring careful multi-variable optimization to balance reliability and performance (Engineering Practice).

At the 28nm node, scaling of the interconnect half-pitch exacerbates the impact of line-to-line parasitic capacitance on circuit speed, making the effective dielectric constant ($k_{eff}$) of the IMD stack a dominant factor in device performance . The T8M3 NDC deposition is specifically engineered for the 28nm planar flow to provide the thinnest possible barrier profile that can still guarantee zero-defect copper containment under high operational electric fields . This step stands out from subsequent dielectric depositions in the M3_PLUS module, such as the PEOX (Plasma-Enhanced Oxide) and Nitride steps, because NDC is the only dielectric layer that makes direct interface contact with the active copper lines, thus requiring a unique focus on interfacial adhesion, native oxide reduction, and diffusion resistance (Engineering Practice).

[High] Interfacial Adhesion Failure and Delamination: Copper CMP leaves trace organic impurities and native copper oxides ($CuO_x$) on the M2 surface . If these are not completely reduced by a pre-deposition plasma treatment, or if the NDC film exhibits high intrinsic compressive stress due to excessive ion bombardment during PECVD, the interfacial shear strength will be insufficient to withstand subsequent thermal cycles up to 400 °C , leading to delamination (peeling) at the Cu/NDC interface .
[High] Copper Silicide Formation and Sheet Resistance Spike: An over-aggressive $NH_3$ or $H_2$ pre-treatment plasma, or improper timing of the organosilane precursor introduction, can lead to the formation of unstable copper silicides ($Cu_xSi$) or high defect density at the interface (Engineering Practice). This interfacial degradation causes a sharp increase in the sheet resistance of the underlying M2 copper lines and promotes vacancy accumulation, severely degrading electromigration (EM) lifetime .
[Medium] Elevated Dielectric Constant (k-value) and RC Penalty: Excessively high nitrogen or hydrogen concentration in the PECVD precursor chemistry can increase the density of highly polarizable $Si-N$ or $N-H$ bonds within the amorphous matrix . This shifts the NDC dielectric constant above its target window, which directly increases the parasitic capacitance of the 28nm interconnect lines and causes severe $RC$ delay degradation .
[Medium] Stress Migration and Voiding: High mechanical stress in the NDC film, coupled with thermal expansion mismatches between copper and the dielectric stack, can generate high localized triaxial tensile stress gradients within the M2 Cu lines (Engineering Practice). During subsequent thermal treatments (such as the post-NDC UV curing), this stress drives vacancy diffusion and aggregation along the grain boundaries at the Cu/NDC interface, leading to stress migration voiding and eventual electrical open failures .

NDC (SiCN) deposition establishes a physical barrier that prevents copper diffusion and ambient oxygen reaction .

[High] Interfacial Adhesion Failure and Delamination: Copper CMP leaves trace organic impurities and native copper oxides ($CuO_x$) on the M2 surface . If these are not completely reduced by a pre-deposition plasma treatment, or if the NDC film exhibits high intrinsic compressive stress due to excessive ion bombardment during PECVD, the interfacial shear strength will be insufficient to withstand subsequent thermal cycles up to 400 °C , leading to delamination (peeling) at the Cu/NDC interface .
[High] Copper Silicide Formation and Sheet Resistance Spike: An over-aggressive $NH_3$ or $H_2$ pre-treatment plasma, or improper timing of the organosilane precursor introduction, can lead to the formation of unstable copper silicides ($Cu_xSi$) or high defect density at the interface (Engineering Practice). This interfacial degradation causes a sharp increase in the sheet resistance of the underlying M2 copper lines and promotes vacancy accumulation, severely degrading electromigration (EM) lifetime .
[Medium] Elevated Dielectric Constant (k-value) and RC Penalty: Excessively high nitrogen or hydrogen concentration in the PECVD precursor chemistry can increase the density of highly polarizable $Si-N$ or $N-H$ bonds within the amorphous matrix . This shifts the NDC dielectric constant above its target window, which directly increases the parasitic capacitance of the 28nm interconnect lines and causes severe $RC$ delay degradation .
[Medium] Stress Migration and Voiding: High mechanical stress in the NDC film, coupled with thermal expansion mismatches between copper and the dielectric stack, can generate high localized triaxial tensile stress gradients within the M2 Cu lines (Engineering Practice). During subsequent thermal treatments (such as the post-NDC UV curing), this stress drives vacancy diffusion and aggregation along the grain boundaries at the Cu/NDC interface, leading to stress migration voiding and eventual electrical open failures .

28nm Planar FlowPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

28nm Planar FlowPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges