28nm Planar Flow 28nm Process Step

It is typically deposited using Plasma-Enhanced Chemical Vapor Deposition (PECVD) or Low-Pressure Chemical Vapor Deposition (LPCVD) at low thermal budgets to prevent the premature diffusion of implanted S/D dopants .

In advanced planar CMOS technologies, Stress Memorization Technology (SMT) is integrated into the Middle-of-Line (MOL) flow to selectively boost nMOSFET channel mobility . Positioned directly after the source/drain (S/D) extension and deep junction implants (PIO S/D Impla

nt 2 and 3) and photoresist stripping, the SMT Oxide Deposition step marks the beginning of the SMT module . The primary integration purpose of this oxide layer is to act as a conformal stress-buffer, screening layer, and highly selective chemical etch-stop liner before the deposition of the highly-stressed SMT Nitride capping layer . This temporary stack remains on the wafer during the subsequent SMT Rapid Thermal Anneal (RTA) and is selectively stripped during the SMT Nitride Removal step prior to contact formation . By introducing this oxide, the underlying active silicon, newly formed S/D junctions, and fragile gate spacer structures are protected from direct mechanical damage, physical sputtering, and chemical attack during the nitride deposition and stripping steps .

The physical mechanism of SMT relies on solid-state recrystallization, thermal expansion, and viscoelastic stress coupling . Prior to SMT deposition, a pre-amorphization implant (PAI) using heavy species such as germanium or arsenic amorphizes the upper region of the polycrystalline silicon (poly-Si) gate . During the subsequent high-temperature RTA, the poly-Si undergoes solid-phase epitaxial recrystallization and grain growth under the physical constraint of the temporary oxide-nitride capping stack . As the grain structure reforms, the local volume changes and thermal expansion generate significant mechanical stress, which is governed by anisotropic linear elastic relations ($\sigma_i = C_{ij}\varepsilon_j$) and quasi-static force balance . This mechanical deformation is transferred through the thin oxide and "frozen" into the poly-Si gate and the underlying channel . Upon removal of the capping layers, the residual strain persists due to geometric constraints , creating a vertical compressive and lateral tensile strain in the channel . This strain alters the silicon lattice's periodic potential and shifts the energy band structure ($E-k$ relationship) via the Schrödinger wave equation , which lifts the degeneracy of the conduction band valleys, lowers the electron effective mass, suppresses intervalley phonon scattering, and ultimately boosts electron mobility .

The choice of material and deposition method for the SMT oxide is driven by a critical trade-off between mechanical coupling efficiency, thermal budget, and etch selectivity . Unlike other oxide depositions in the flow—such as STI HARP Liner/Oxide Depositions which utilize high-ozone TEOS-based processes for high-aspect-ratio gap-fill, or CB and RV Silane Oxide Depositions which form permanent passivation and interlayer dielectrics —the SMT oxide must be temporary, thin, and highly conformal . It is typically deposited using Plasma-Enhanced Chemical Vapor Deposition (PECVD) or Low-Pressure Chemical Vapor Deposition (LPCVD) at low thermal budgets to prevent the premature diffusion of implanted S/D dopants . The deposition process parameters must be optimized because a thicker or less dense oxide layer exhibits greater viscoelastic relaxation during high-temperature annealing, which dampens the mechanical stress transfer from the SMT nitride to the channel . Conversely, an excessively thin oxide layer provides insufficient protection during the subsequent hot phosphoric acid or dry etch steps used for SMT Nitride Removal, risking active area pitting and spacer erosion .

At the 28nm planar node, SMT becomes highly critical as traditional geometrical scaling can no longer yield sufficient drive current performance on its own . SMT is exceptionally valuable at this node because its layout dependency is relatively low compared to permanent stress liners, making it compatible with tight 28nm gate pitches . Furthermore, by using SMT selectively, the nMOS performance can be enhanced by over 15% without incurring the severe pMOS mobility degradation that occurs when high-tensile stress liners are applied globally .

[High] Stress Dampening and Performance Loss: If the SMT oxide layer is deposited with excessive thickness or exhibits low mechanical density, the film undergoes severe viscoelastic relaxation during the subsequent high-temperature rapid thermal anneal . This relaxation dampens the mechanical coupling between the highly-stressed SMT nitride capping layer and the underlying amorphized poly-Si gate , preventing efficient stress transfer . Consequently, the channel strain cannot be effectively "memorized" after the capping layers are stripped, leading to a failure to achieve the target electron mobility and drive current enhancement .
[Medium] Active Area Pitting and Spacer Erosion: If the SMT oxide film has poor step coverage or suffers from thickness non-uniformity at the base of the gate electrodes, the film may be extremely thin or contain microscopic voids near the gate spacer edge . During the subsequent SMT Nitride Removal step, the wet chemical etchant (typically hot phosphoric acid) or dry reactive ion etching can break through these weak oxide regions . This leads to severe pitting of the underlying silicon active S/D regions, erosion of the gate spacer, and increased parasitic contact leakage or junction leakage .
[Medium] Gate Leakage Degradation and Oxide Defect Generation: The intense mechanical stress fields transferred through the SMT stack during rapid thermal annealing can induce structural defects and trap states within the ultra-thin gate dielectric . If the SMT oxide liner fails to uniformly distribute the stress, localized high-stress concentrations can generate bulk oxide traps and interface states . These defects enhance trap-assisted Poole-Frenkel conduction under operating electric fields , resulting in elevated gate leakage current and degraded Time-Dependent Dielectric Breakdown (TDDB) reliability .
[Medium] Pre-Activation Dopant Diffusion: SMT oxide deposition processes that utilize high thermal budgets can cause premature diffusion of the newly implanted S/D extension and halo dopants before the dedicated spike annealing step . This unwanted thermal budget consumption alters the lateral dopant profiles, worsening short-channel effects, shifting the device threshold voltage ($V_{th}$), and degrading the subthreshold swing ($S$) .
[Low] Hydrogen-Induced Interface Instability: PECVD precursors (such as silane) typically introduce hydrogen into the SMT oxide and nitride films . During high-temperature annealing, hydrogen atoms dissociate from Si-H or N-H bonds and diffuse to the gate oxide interface . While minor hydrogen accumulation can passivate interface dangling bonds ($P_b$ centers) , excessive hydrogen diffusion and subsequent thermal desorption can generate permanent interface states, leading to Hot Carrier Injection (HCI) degradation and accelerated Bias Temperature Instability (BTI) over the device lifetime .

[High] Stress Dampening and Performance Loss: If the SMT oxide layer is deposited with excessive thickness or exhibits low mechanical density, the film undergoes severe viscoelastic relaxation during the subsequent high-temperature rapid thermal anneal . This relaxation dampens the mechanical coupling between the highly-stressed SMT nitride capping layer and the underlying amorphized poly-Si gate , preventing efficient stress transfer . Consequently, the channel strain cannot be effectively "memorized" after the capping layers are stripped, leading to a failure to achieve the target electron mobility and drive current enhancement .
[Medium] Active Area Pitting and Spacer Erosion: If the SMT oxide film has poor step coverage or suffers from thickness non-uniformity at the base of the gate electrodes, the film may be extremely thin or contain microscopic voids near the gate spacer edge . During the subsequent SMT Nitride Removal step, the wet chemical etchant (typically hot phosphoric acid) or dry reactive ion etching can break through these weak oxide regions . This leads to severe pitting of the underlying silicon active S/D regions, erosion of the gate spacer, and increased parasitic contact leakage or junction leakage .
[Medium] Gate Leakage Degradation and Oxide Defect Generation: The intense mechanical stress fields transferred through the SMT stack during rapid thermal annealing can induce structural defects and trap states within the ultra-thin gate dielectric . If the SMT oxide liner fails to uniformly distribute the stress, localized high-stress concentrations can generate bulk oxide traps and interface states . These defects enhance trap-assisted Poole-Frenkel conduction under operating electric fields , resulting in elevated gate leakage current and degraded Time-Dependent Dielectric Breakdown (TDDB) reliability .
[Medium] Pre-Activation Dopant Diffusion: SMT oxide deposition processes that utilize high thermal budgets can cause premature diffusion of the newly implanted S/D extension and halo dopants before the dedicated spike annealing step . This unwanted thermal budget consumption alters the lateral dopant profiles, worsening short-channel effects, shifting the device threshold voltage ($V_{th}$), and degrading the subthreshold swing ($S$) .
[Low] Hydrogen-Induced Interface Instability: PECVD precursors (such as silane) typically introduce hydrogen into the SMT oxide and nitride films . During high-temperature annealing, hydrogen atoms dissociate from Si-H or N-H bonds and diffuse to the gate oxide interface . While minor hydrogen accumulation can passivate interface dangling bonds ($P_b$ centers) , excessive hydrogen diffusion and subsequent thermal desorption can generate permanent interface states, leading to Hot Carrier Injection (HCI) degradation and accelerated Bias Temperature Instability (BTI) over the device lifetime .

28nm Planar FlowPreview

Process Cross-Section

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In depth

Risks & Challenges

28nm Planar FlowPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges