28nm Planar Shallow Trench Isolation Process Flow: Principles, Integration Logic, and Mechanisms

Role in the Complete Flow

The 28nm Planar shallow trench isolation (STI) module is one of the earliest structural-defining stages in the overall 28nm Planar process flow. It receives a silicon substrate that has undergone initial pad-stack preparation—typically a thin thermally grown pad oxide topped with a deposited silicon nitride hard-mask layer. Its central objective is to carve isolation trenches into the silicon substrate and refill them with high-quality dielectric material so that adjacent transistor active regions are electrically and structurally separated.

In broader integration, the STI process flow serves as the geometric anchor for active-area patterning and device density scaling. Shallow trench isolation replaces older isolation techniques because it shows much better performance than the conventional local oxidation of silicon (LOCOS) method which causes bird’s beak-like structures . The isolation trenches set the lateral boundaries for every active region, meaning that any dimensional or slope deviation introduced during trench definition propagates directly into effective channel-width variations, threshold-voltage shifts, and junction leakage margins in downstream modules.

The STI module also establishes the topographic baseline for subsequent chemical mechanical polishing (CMP) operations. Because the trench-fill oxide overburden must be polished back and stopped cleanly on the silicon nitride hard-mask surface, the step-height uniformity and profile control achieved within the STI module dictate the CMP process window and, by extension, the lithographic fidelity of subsequent active-area patterning and gate definition.

Entry State and Sequence Logic

Upstream Dependencies

Prior to the STI module, the wafer undergoes pad-stack preparation. In the pad-stack preparation, the presence of a very thin silicon nitride stop layer (deposited on another thin pad oxide layer to control film stress) is an essential and integral part of the process [P1]. The pad oxide serves as a strain-relief interface, while the silicon nitride layer functions as both a hard mask during silicon etching and a CMP polish-stop layer. The interface quality between pad oxide and silicon substrate is critical; inadequate oxide quality or interface contamination can induce stress-related crystal dislocations during subsequent thermal steps.

The 28nm Planar well formation process flow may precede or follow STI formation depending on the integration scheme. When well implants are performed prior to STI, trench etching must accommodate subtle variations in silicon etch rate across different doping concentrations. Conversely, when well formation follows STI, the field oxide geometry self-aligns the well and channel-stop implants, preventing lateral dopant diffusion into adjacent active channels.

Sequence Logic Within the Module

The STI module follows a strict physical and chemical sequence: lithographic photoresist patterning defines trench openings, an anisotropic reactive ion etch (AA Etch) transfers the pattern through the cap oxide and nitride hard mask while stopping on or just above the silicon substrate, preparing a hard-mask opening that guides the subsequent silicon trench etch. After the hard-mask stack is opened, the silicon trench etch carves the isolation trenches directly into the crystalline silicon substrate. Following trench definition, photoresist is stripped, and the trench surface undergoes wet pre-cleansing.

The dielectric fill sequence begins with thermal liner oxidation on the exposed silicon sidewalls and bottom. A deposited liner is then added, followed by an isotropic etch-back step to optimize sidewall slope prior to main oxide gap fill. After high-aspect-ratio oxide deposition, the dielectric is densified through a high-temperature thermal anneal. Chemical mechanical polishing then removes the overburden oxide, stopping on the pad nitride layer. A post-CMP anneal stabilizes the oxide, and a wet etching step adjusts the STI oxide height relative to the nitride surface before final pad nitride removal and cleaning.

A key integration requirement is the chemical selectivity between the silicon etch and the nitride hard mask. The nitride mask must remain intact throughout the trench etch step to prevent lateral widening of the trench top and unwanted erosion of the active region width.

Physical and Chemical Mechanisms

Plasma Etch Fundamentals for Trench Definition

Trench definition relies on plasma-assisted etching in a low-pressure discharge reactor. Controlled material removal occurs through synergistic interactions between energetic ions and chemical radicals. Anisotropic etch directionality is usually related to physical effects in etching such as ion bombardment and sputtering [T1]. Chemical radicals adsorb on the exposed surface and react to form volatile byproducts that are evacuated by the vacuum system.

For the silicon nitride and pad oxide pattern transfer, fluorocarbon-based chemistry (such as CF4/CH2F2) is used to achieve directional profiles and selectivity against the underlying photoresist and silicon. Langmuir–Hinshelwood kinetic models describe how radical adsorption coverage and ion flux balance govern local etch rates, enabling precise pattern transfer with minimal bias.

Active Area Etch and Silicon Trench Formation

The AA Etch step transfers the active-area definition into the underlying hard-mask oxide stack, stopping cleanly on or slightly above the silicon substrate to preserve substrate integrity. This forms a precise hard-mask opening that guides the subsequent silicon trench etch, ensuring that the isolation structure is self-aligned to the active region layout. Once the hard mask is opened, the silicon trench etch defines the depth, sidewall taper, and profile of the isolation trench in crystalline silicon.

To prevent void formation during dielectric gap fill while maximizing active area density, the silicon sidewalls are etched to a slightly tapered angle rather than a purely vertical profile. Additionally, the top and bottom corners of the trench must be smoothly rounded to prevent localized electric-field concentration.

Bromine-based chemistries (e.g., HBr/O2/Cl2) are typically employed for silicon trench etching. Volatile SiBr4 byproducts interact with oxygen species to form a thin silicon oxy-bromide passivation layer on the trench sidewalls. This passivation layer inhibits lateral chemical etching while vertical ion bombardment continues at the trench bottom, maintaining anisotropic profile control. Tuning the balance between ion energy, radical concentration, and passivation deposition yields the desired tapered profile and rounded bottom corners.

Liner Oxide Growth and Corner Rounding

Following trench etching, wet cleaning removes etch residues and prepares the silicon surface for thermal liner oxidation. High-temperature thermal liner oxidation grows a thin silicon dioxide film on the trench sidewalls and bottom. This thermal step repairs surface damage caused by plasma ion bombardment during trench etching and creates a high-quality SiO2/Si interface with low fixed oxide charge and interface trap density.

At elevated thermal oxidation temperatures, viscoelastic flow of silicon dioxide relaxes localized mechanical stress at geometric sharp edges. Combined with a controlled pad oxide pullback step, thermal oxidation rounds the upper trench corners. This corner rounding prevents sharp-corner electric field enhancement, suppressing parasitic edge-channel conduction and eliminating double-hump subthreshold characteristics in the transistor.

Gap-Fill Chemistry and Void Prevention

At the 28nm node, increasing aspect ratios make single-step oxide gap fill susceptible to premature pinch-off and void formation. To address this, a Liner–Etch-back–Gap-fill strategy is integrated into the module sequence. After initial liner deposition, an in-situ or downstream plasma etch-back (such as NH3/NF3 remote plasma chemistry) reacts with the oxide surface to form an intermediate ammonium fluorosilicate salt. Subsequent thermal sublimation removes material preferentially from the trench neck, opening the trench top.

Because this etch-back mechanism is self-limiting and diffusion-controlled, it reshapes the trench entrance profile without damaging the underlying silicon substrate. Following profile reshaping, high-density plasma or high-aspect-ratio process SACVD oxide fills the trench volume from the bottom up, achieving void-free dielectric isolation.

CMP Planarization Mechanisms

After dielectric gap fill and high-temperature densification anneal, chemical mechanical polishing removes excess oxide overburden. High-selectivity slurry (HSS) CMP utilizes ceria-based abrasives with chemical additives that selectively passivate the silicon nitride surface. The chemical interaction between ceria nanoparticles and silicon dioxide forms Ce–O–Si bonds, enabling rapid oxide removal under mechanical shear, whereas additive adsorption on silicon nitride dramatically suppresses nitride removal.

The Preston equation governs the phenomenological removal rate:

RR = K_P * P * v

where K_P is the Preston coefficient reflecting chemical and mechanical interactions, P is applied polishing pressure, and v is relative platen velocity. High selectivity between oxide and nitride limits nitride hard-mask erosion and suppresses oxide dishing across variable active-area pattern densities.

Interfaces and Failure Propagation

Upstream Interface: Pad Stack Quality

The physical integrity of the pad stack dictates the process window for the STI module. If the pad oxide is deficient in thickness or stoichiometry, excessive mechanical stress from the nitride layer transfers into the silicon substrate, generating dislocations that cause junction leakage. Conversely, an overly thick nitride layer increases film stress and induces wafer bow, degrading lithography alignment accuracy.

Intra-Module Interface: Etch-to-Fill Transition

The interface between trench etch profile definition and dielectric gap fill represents a primary yield boundary. An overly vertical trench profile promotes premature oxide pinch-off, resulting in internal voids. Excessively tapered sidewalls conserve gap-fill margin but reduce effective transistor channel width and compromise packing density. The etch-back step must be carefully tuned to avoid micro-trenching or over-etching into active active-area boundaries.

Downstream Interface: CMP-to-Lithography

The surface state following STI CMP directly impacts post-isolation lithography and well implants. Non-uniform residual nitride thickness translates into topographic step-height variations across the die, reducing depth-of-focus margins during gate lithography. Dishing in wide STI field regions creates local depressions that trap conductive residues during subsequent gate and contact metal patterning, leading to inter-line short circuits.

Failure Propagation Pathways

• Incomplete Gap Fill: Unfilled voids within the STI trench trap moisture and chemical residues during subsequent wet cleans. Later polysilicon or metal gate deposition can fill these voids, creating permanent low-resistance leakage paths between adjacent active regions.
• Inadequate Corner Rounding: Sharp trench top corners cause localized electric field concentration, lowering the local threshold voltage at the channel edge and triggering parasitic subthreshold leakage ("double-hump" Id–Vg curves).
• CMP Over-polishing and Dishing: Excessive nitride erosion during CMP exposes the underlying active silicon to chemical attack and surface roughening, degrading gate oxide breakdown voltage and channel mobility.

Walk the Real Module

To explore how these physical and chemical principles operate within a real process flow, you can Open STI Step 8 in the interactive flow. This step initiates the active area pattern transfer, stopping on or just above silicon to prepare the hard-mask opening that guides the sub-surface isolation trench formation.

Tracing the topology sequence through thermal liner oxidation, oxide gap fill, etch-back, CMP planarization, and pad nitride strip highlights how each unit step's exit state forms the entry state for the next, reinforcing the strict integration logic required for 28nm planar device isolation.

Related Learning Paths

To deepen your understanding of integration dependencies adjacent to the STI module, review these related technical articles:

• The 28nm Planar process flow overview contextualizes STI within the full manufacturing flow from substrate preparation to metallization.
• The 28nm Planar active-area definition process flow details photolithography and hard-mask pattern transfer principles prior to trench etching.
• The 28nm Planar well formation process flow explains how well implants self-align to STI geometries and manage channel-stop isolation.

Future Outlook

As CMOS scaling progressed beyond the 28nm planar node into 3D FinFET architectures, isolation schemes evolved significantly. In FinFET technology, active fins and isolation trenches are etched simultaneously using shared multi-patterned hard masks. This requires dual-stage etch profiles that maintain vertical fin sidewalls while providing tapered trench bottoms for dielectric gap fill.

In advanced planar derivative nodes, self-limiting atomic layer etching (ALE) and flowable chemical vapor deposition (FCVD) have refined trench profile control and void-free fill capabilities. Furthermore, research into STI-embedded buried power rails leverages isolation trench volume to route power supply networks beneath active devices, transforming traditional passive isolation structures into functional 3D interconnect pathways.