28nm Planar Shallow Trench Isolation Process Flow: Principles, Integration Logic, and Mechanisms

Role in the Complete Flow

The 28nm Planar shallow trench isolation module is one of the earliest structural-defining steps in the entire 28nm Planar process flow [P3]. It receives a silicon substrate that has already undergone initial pad-stack preparation—typically a thin pad oxide followed by a silicon nitride hard-mask layer—and its central mission is to carve isolation trenches into the silicon substrate and refill them with dielectric material so that adjacent transistor active regions are electrically and structurally separated [T1][P3]. What this module must deliver downstream is a planarized, void-free isolation structure with rounded corners, controlled sidewall slopes, and a high-quality silicon-to-dielectric interface, all of which become the foundation upon which well implants, gate stack formation, and source/drain engineering are built [P3].

In the broader integration picture, the STI module process flow serves as the geometric anchor for device density scaling [P3]. At the 28nm node, the replacement of older local oxidation of silicon (LOCOS) schemes with STI is driven by the need for near-zero field encroachment, superior latch-up immunity, and excellent topographic planarity for subsequent lithographic patterning [P3][P4]. The isolation trenches define the lateral boundaries of every active area, meaning that any dimensional or profile deviation introduced here propagates directly into channel-width control, threshold-voltage uniformity, and junction isolation margin in downstream modules [T2].

The 28nm shallow trench isolation module also establishes the topographic baseline for chemical mechanical polishing (CMP) steps that follow [P4]. Because the trench-fill oxide must be planarized back to the nitride hard-mask surface, the step-height uniformity achieved within the STI module constrains the process window for the CMP operation and, by extension, the lithographic fidelity of the first active-area patterning step that defines transistor dimensions [P4].

Entry State and Sequence Logic

Upstream Dependencies

Before the STI module begins, the wafer must have a properly constructed pad stack [P3]. This stack consists of a thermally grown pad oxide serving as a stress-relief buffer, topped by a deposited silicon nitride layer that functions as both a hard mask for trench etching and a polish-stop layer for CMP [T1][P1]. The pad oxide quality matters because it governs the interfacial stress between silicon and nitride; if this interface is compromised, subsequent thermal cycles can inject defects into the silicon substrate [T1].

The 28nm Planar well formation process flow may occur either before or after STI formation depending on the integration scheme [P2]. When well implants precede STI, the trench etch must account for different doping concentrations across the wafer, which can subtly influence etch rates through doping-dependent surface chemistry [P2]. When well implants follow STI, the isolation geometry itself helps self-align the implants and suppress lateral diffusion [P3].

Sequence Logic Within the Module

The STI module process flow follows a tightly sequenced logic: photoresist patterning defines the trench openings, then successive etch steps transfer the pattern through the nitride and pad oxide, followed by the active area etch into the silicon substrate itself [T1]. After trench formation, a thermal liner oxide is grown on the trench sidewalls and bottom, the trench is filled with deposited oxide, and finally CMP planarizes the surface [P1][P3].

The critical sequence dependency is that the SiN etch and subsequent silicon etch must be decoupled in terms of chemistry and selectivity [P2]. The nitride hard mask must survive the silicon etch step intact, which demands that the silicon etch chemistry exhibits high selectivity to silicon nitride [P1]. This selectivity requirement is a direct consequence of the integration logic: if the hard mask erodes during silicon etching, the trench opening widens uncontrollably and the active area shrinks, directly reducing transistor drive current [T1].

Physical and Chemical Mechanisms

Plasma Etch Fundamentals for Trench Definition

The trench definition sequence relies fundamentally on plasma etching, where controlled material removal occurs in a low-pressure discharge environment through synergistic interactions between ions, radicals, and excited species with the solid surface [P1]. High-energy ions accelerated by the sheath electric field provide directional kinetic energy that breaks surface bonds and enhances reactivity, while neutral radicals adsorb and react at the surface to form volatile products that are pumped away [P1]. The balance between physical sputtering and chemical reaction determines the anisotropy, selectivity, and damage characteristics of each etch step [P1].

For the SiN etch and pad oxide etch steps, fluorocarbon-based chemistries are commonly employed because they provide the necessary selectivity between silicon nitride, silicon oxide, and the underlying silicon substrate [P1][T1]. The Langmuir–Hinshelwood surface kinetics govern the reaction rates, meaning that adsorption coverage of reactive species on the surface becomes the rate-limiting factor [P1]. By tuning ion energy, radical flux, and surface temperature, engineers can achieve the required balance between anisotropic profile control and material selectivity [P1].

Active Area Etch: Silicon Trench Formation

The AA etch—that is, the active area etch into crystalline silicon—is arguably the most mechanistically demanding step in the STI module [P3]. The AA Etch integration principles demand a trench profile that is nearly vertical to preserve active area width, yet slightly tapered to facilitate void-free gap fill [T1][P3]. Additionally, the top and bottom corners of the trench must be rounded to avoid electric field concentration that would otherwise create parasitic conduction paths and the well-known double-hump Id–Vg characteristic [P3].

Bromine-based plasma chemistries are often selected for the silicon etch because they provide excellent anisotropy and sidewall passivation through the formation of a protective sidewall polymer layer [T1]. The passivation mechanism works as follows: volatile silicon etch products react with passivating species to deposit a thin polymer film on the trench sidewalls, protecting them from lateral etching while the bottom of the trench continues to be etched by vertically directed ions [P3]. This interplay between chemical etching, ion bombardment, and sidewall passivation is what enables the controlled, slightly tapered profile required for 28nm shallow trench isolation [P1][T1].

Liner Oxide Growth and Corner Rounding

After the trench is etched into silicon, a thermal liner oxide is grown on the exposed silicon surfaces [P3]. This step serves dual purposes: it creates a high-quality silicon-to-silicon-dioxide interface with low electrical charge density, and at elevated temperatures the viscoelastic flow properties of the oxide promote corner rounding at both the top and bottom of the trench [T1]. The corner rounding is not merely cosmetic—it directly addresses the electric field concentration that can be understood through the Poisson equation with interface boundary conditions, where sharp corners create localized field enhancements that produce parasitic channels [P3].

Pad oxide undercut, performed prior to liner oxidation, provides additional geometric freedom for corner rounding [P3]. By partially removing the pad oxide beneath the nitride hard mask, the oxidation front can grow more freely at the trench top corners, increasing the radius of curvature while minimizing sacrifice of active area [P3]. This technique exemplifies how structural design at the pad-stack level is leveraged to control device physics outcomes at the isolation level [P3].

Gap-Fill Chemistry and Void Prevention

At the 28nm node, the increased aspect ratio of STI trenches makes void-free gap fill particularly challenging [P2]. Conventional sub-atmospheric chemical vapor deposition (SACVD) of silicon dioxide using TEOS/ozone chemistry, which served well at larger nodes, begins to show filling limitations because the more vertical sidewalls at 28nm dimensions cause premature pinch-off at the trench opening [P2]. The mechanism is geometric: as deposited oxide nucleates and grows on opposing sidewalls, vertical walls cause the opening to close before the trench bottom is fully filled, trapping a void [P3].

An innovative solution is the Liner–Etch-back–Gap-fill (L-E-G) strategy, which introduces an intermediate etch-back step between liner deposition and main gap fill [P2]. This etch-back uses downstream plasma generated from NH₃/NF₃ chemistry, where active species react with the SiO₂ liner to form a sublimable ammonium salt [P2]. During a subsequent heating step, this salt sublimates, gently removing oxide from the liner surface and reshaping the sidewall slope to be more favorable for void-free fill [P2]. The etch process is self-limiting because it is governed by diffusion of active species through the growing salt layer, leading to a time-dependent etch-rate slowdown [P2].

CMP Planarization Mechanisms

The final planarization step in the STI module relies on CMP to remove the oxide overburden and stop on the nitride hard mask [P4]. Two fundamentally different CMP philosophies exist at the 28nm node: high selective slurry (HSS) CMP, where material removal is dominated by chemically enhanced abrasion through ceria-based Ce–O–Si interactions with silicon oxide, and fixed abrasive (FA) CMP, where mechanically immobilized ceria abrasives remove material primarily through micro-cutting and plowing [P4].

In HSS CMP, the chemical affinity between ceria and silicon oxide provides inherent selectivity over silicon nitride, reducing sensitivity to local pattern density and dummy layout design [P4]. In FA CMP, the fixed abrasives make local contact mechanics and pressure distribution dominant, causing stronger pattern-density dependence and greater sensitivity to dummy pattern geometry [P4]. The Preston equation governs both approaches, where removal rate scales with applied pressure and relative velocity, but the chemical reaction kinetics at the surface modify this relationship differently for each scheme [P4].

Interfaces and Failure Propagation

Upstream Interface: Pad Stack Quality

The quality of the pad oxide and nitride hard mask directly constrains the STI module's process window [P4]. If the pad oxide is too thin or of poor interfacial quality, stress transfer from the nitride to the silicon substrate during thermal cycles can generate crystal defects that act as leakage paths [T1]. Conversely, if the nitride is too thick, the residual stress can cause substrate warpage that degrades lithographic overlay accuracy during trench patterning [P3]. The AA Etch integration principles require that the pad stack be mechanically robust enough to survive the entire trench etch sequence without measurable erosion [P3].

Intra-Module Interface: Etch-to-Fill Transition

The most critical intra-module interface is the transition from trench etching to gap fill [P2]. A trench profile that is too vertical will cause void formation during oxide deposition, while a profile that is too tapered wastes active area and reduces isolation depth [P3][P2]. The trench bottom must be flat and rounded—sharp bottoms concentrate stress and can nucleate dislocations during subsequent thermal processing [P3]. The L-E-G strategy addresses this interface by reshaping the liner profile between etch and fill, but it introduces its own tradeoff: the etch-back exhibits significant loading effects on patterned wafers, meaning that dense and isolated trenches etch at different rates, constraining uniformity [P2].

Downstream Interface: CMP-to-Lithography

The STI CMP step must deliver a surface that is sufficiently planar for the first post-isolation lithography step [P4]. Non-uniform nitride thickness after CMP directly translates to step-height variations that degrade focus-exposure dose latitude in subsequent lithographic patterning [P4]. Trench oxide dishing—a localized depression in the oxide surface within wide trench regions—creates topographic non-planarity that can affect gate definition over isolation regions [P4]. Dummy active area patterns are introduced specifically to homogenize the pressure and velocity fields during CMP, mitigating these density-dependent effects [P4].

Failure Propagation Pathways

When the STI module fails to deliver a void-free isolation structure, the consequences propagate far downstream [T1]. Voids within the trench fill oxide create localized dielectric weakness that manifests as isolation leakage between adjacent transistors, potentially causing circuit malfunction or reliability failure under bias stress [P2]. Inadequate corner rounding produces parasitic edge conduction channels that alter threshold voltage characteristics and degrade subthreshold swing, directly impacting the Ion/Ioff tradeoff that governs both device speed and static power [P3][T2]. Stress-induced defects from excessive thermal budgets or aggressive liner oxidation can create crystallographic defects in the silicon substrate that increase junction leakage and reduce carrier mobility in adjacent active regions [P3].

Walk the Real Module

To see how these principles translate into actual process steps, you can Open STI Step 8 in the interactive flow (Engineering Practice). This interactive module lets you trace the exact sequence of operations—from pad stack preparation through trench etching, liner oxidation, gap fill, and CMP planarization—that constitute the 28nm Planar STI module [P2]. Walking through the steps in order makes the integration logic tangible: each step's entry state is the previous step's exit state, and the selectivity, profile, and uniformity requirements at each transition become visible as concrete process decisions rather than abstract principles (Engineering Practice).

The interactive flow also illustrates how the 28nm Planar active-area definition process flow interfaces with the STI module [P2]. The active area etch step within STI is where the isolation trenches and active regions are physically separated in the silicon substrate—a step whose profile quality directly determines the effective channel width of every transistor on the die [P3].

Related Learning Paths

Engineers studying the 28nm Planar STI module should explore several adjacent topics to build a complete integration picture:

• The 28nm Planar process flow article provides the overarching module sequence and shows where STI sits relative to well formation, gate stack, and source/drain modules [P2].
• The 28nm Planar active-area definition process flow article dives deeper into the lithographic and etch principles that define the active area etch step, including how photoresist patterning and hard-mask strategy interact with the STI trench profile [P2].
• The 28nm Planar well formation process flow article explains how well implants are integrated relative to STI, and how the isolation geometry self-aligns channel-stop and well implants to suppress latch-up and lateral diffusion [P2].

Future Outlook

As planar CMOS scaling approached and then moved beyond the 28nm generation, the STI module faced increasingly severe challenges [P3]. The transition to FinFET architectures fundamentally changed the isolation paradigm: in bulk-silicon FinFET flows, the fins and isolation trenches are etched simultaneously using a shared hard mask, and the etch is carried out in two stages—the first creating the vertical profile needed for the fins, followed by a second step creating the tapered profile needed for the trench [P1]. This dual-profile requirement places even greater demands on etch chemistry control and sidewall passivation than the planar STI module [P2].

For those continuing to optimize planar STI at mature nodes, emerging directions include the development of self-limiting, low-damage etch-back processes that can reshape trench profiles without ion bombardment damage [P2], and advanced CMP chemistries that further reduce pattern-density sensitivity [P4]. There is also growing interest in buried interconnect structures that leverage STI trenches as conduits for underground signal lines, transforming the isolation module from a purely passive structure into an active interconnect pathway [A1][A2]. This concept embeds conductive lines within the STI trench, isolated from the silicon substrate by dielectric layers, reducing parasitic capacitance and enabling three-dimensional interconnect layering below the device surface [A2].