40nm BSI CMOS Image Sensor Backside Passivation Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

In a 40nm BSI CMOS Image Sensor (CIS) process flow, the backside passivation (BKPAS) module occupies a critical position between backside wafer thinning and backside optical element formation. The module receives a wafer whose active silicon layer has been thinned so that incident illumination can directly enter the photodiode substrate. In backside illumination configurations, the semiconductor substrate is thinned down so that light can be directly absorbed within the active region without gate absorption [T2]. The primary task of BKPAS is to deliver a chemically and electrically stable interface that minimizes surface recombination and dark current before subsequent color filter array and microlens deposition steps.

The fundamental purpose of the BKPAS module is to suppress dark current generated at the thinned backside silicon surface. When the 40nm BSI CIS substrate is thinned, the crystal lattice termination at the backside creates a high density of dangling bonds and structural disorder, introducing energy states within the silicon bandgap. These interface traps act as generation–recombination centers, increasing dark current and degrading quantum efficiency. The passivation stack must chemically terminate these dangling bonds and, through fixed charges in the dielectric layers, induce band bending that repels minority carriers away from the interface.

From an integration perspective, the BKPAS module bridges two distinct processing regimes. Upstream, it depends on the 40nm BSI CMOS Image Sensor backside wafer thinning process flow to produce a clean, low-damage silicon surface. Downstream, it provides an electrically stable platform for optical stack deposition and patterning of backside structures. The passivation quality directly determines whether the image sensor can achieve the dark current and quantum efficiency targets set by the overall 40nm BSI CMOS Image Sensor process flow.

The module's output is an engineered interface: a dielectric stack whose chemical bonding, fixed charge density, and trap characteristics define the electrostatic landscape at the backside silicon surface. This interface must remain stable through all subsequent thermal treatments and process steps in the backside integration sequence.

Entry State and Sequence Logic

Upstream Dependencies

The BKPAS module receives the wafer after backside thinning has reduced the silicon substrate to the thickness required for optical absorption. The entry surface condition is paramount: residual crystal damage, contamination, or micro-roughness from the thinning process propagates into the passivation interface and degrades its electrical quality. Thinning must produce a surface with minimal sub-surface damage, as subsequent atomic layer deposition (ALD) and chemical vapor deposition (CVD) steps are conformal and replicate underlying surface morphology.

The sequence logic demands that the wafer enter BKPAS with a surface chemically prepared to remove native oxide and thinning residues. This preparation step is critical because the first dielectric layer deposited in BKPAS forms the primary silicon–dielectric interface, governing the interface trap density ($D_{it}$) that controls surface generation dark current.

Downstream Delivery

After BKPAS completion, the wafer proceeds to backside optical element formation. The passivation stack must survive subsequent thermal treatments without degradation of its fixed charge characteristics or hydrogen passivation. In 40nm BSI CIS integration, the passivation layer also serves as a foundation for hard mask layers used during backside patterning, such as color filter array framing or contact opening.

The 40nm BSI CMOS Image Sensor backside substrate-contact integration process flow depends on the passivation layer's integrity, as substrate contacts must penetrate or interface with the passivation stack without introducing leakage paths.

Sequence Ordering Rationale

Placing BKPAS immediately after thinning and prior to optical element deposition reflects a fundamental integration requirement: passivation must be applied to a freshly cleaned silicon surface to maximize chemical bond formation. Delay introduces native oxide regrowth and atmospheric contamination, both of which increase interface trap density. Simultaneously, BKPAS must precede optical stack formation because the passivation layer forms part of the optical path, and its refractive index and transparency influence total quantum efficiency.

Physical and Chemical Mechanisms

Chemical Passivation

Chemical passivation in the 40nm BSI CIS BKPAS module operates by terminating silicon dangling bonds at the thinned backside surface. Uncoordinated surface silicon atoms create energy states within the bandgap that serve as generation–recombination centers. The primary chemical mechanism forms strong Si–O or Si–H bonds at the interface.

For backend applications, after the wafer contains metal layers, oxide deposition is the necessary option because silicon is not available from underlying films for thermal growth [T1]. In backside processing, thermal oxidation is precluded by the thermal budget of existing frontside metallization, so a thin deposited silicon dioxide (SiO₂) interlayer is used to form Si–O–Si bridge bonds. This interlayer is complemented by forming gas annealing, in which hydrogen species diffuse to the interface and terminate remaining dangling bonds. Thermal treatment in forming gas is widely used after layer deposition to passivate interface states through hydrogen migration [P2].

Field-Effect Passivation

Field-effect passivation exploits fixed charges ($Q_f$) embedded within high-k dielectric materials such as aluminum oxide (Al₂O₃) or tantalum oxide (Ta₂O₅) to create an internal electric field at the silicon surface. This field modifies surface band bending, repelling minority carriers from the interface and suppressing surface recombination velocity.

The physics of this mechanism is rooted in metal–insulator–semiconductor electrostatics. Fixed charges within the dielectric generate an electric field described by Poisson's equation, modifying the surface potential of the underlying silicon. For an n-type photodiode region, negative fixed charges induce hole accumulation at the surface, creating an electrostatic barrier that repels photogenerated electrons away from the surface interface traps.

The Chemical–Field-Effect Tradeoff

A critical interaction governs BKPAS stack optimization: the tradeoff between chemical and field-effect passivation. Increasing the thickness of a SiO₂ interlayer improves chemical passivation by providing complete Si–O bonding, but this same dielectric layer screens the fixed charge in the overlying high-k dielectric, weakening field-effect passivation. Conversely, a thinner SiO₂ interlayer preserves field-effect passivation strength but may leave additional interface traps unpassivated.

This tradeoff arises from dielectric screening effects and charge compensation. Optimizing the passivation stack requires balancing interfacial bonding quality, hydrogen passivation efficiency, and the magnitude and sign of fixed charges in the dielectric stack.

PEALD and Plasma-Induced Damage

Plasma-enhanced atomic layer deposition (PEALD) provides low-temperature conformal coverage on thinned backside surfaces. However, plasma exposure during PEALD can introduce interfacial defects such as additional dangling bonds and oxygen vacancies, which act as interface traps or border traps.

This creates a secondary integration tradeoff: a deposition technique providing high conformality and low thermal budget simultaneously introduces plasma damage that must be repaired through post-deposition curing. Forming gas annealing serves this repair function, though its effectiveness varies with dielectric composition and stack architecture.

PECVD in Passivation Context

Plasma-enhanced chemical vapor deposition (PECVD) is utilized within the BKPAS module for depositing silicon nitride or silicon oxide capping layers. PECVD is selected for its low thermal budget, which is mandatory when frontside interconnects are present. Films deposited by PECVD at low temperatures are often non-stoichiometric and contain hydrogen, which can contribute beneficially to interface passivation during subsequent thermal processing.

Interfaces and Failure Propagation

Silicon–Dielectric Interface

The primary interface in the BKPAS module is the silicon–dielectric boundary. Interface trap density at this boundary controls dark current, as these traps provide generation–recombination pathways for carriers. Inadequate chemical passivation manifests as elevated dark current, reducing the signal-to-noise ratio and degrading low-light imaging performance.

The interface quality also influences pinned photodiode operation. In a pinned photodiode, a surface layer pins the surface potential, suppressing dark current from interface states. The BKPAS passivation stack must remain compatible with surface potential pinning, as fixed charges that alter the surface potential can compromise sensor noise performance.

Dielectric–Dielectric Interfaces

In multilayer passivation stacks, the interface between the SiO₂ interlayer and high-k capping dielectrics introduces potential failure pathways. Charge trapping at internal dielectric boundaries can lead to border trap accumulation, causing hysteresis or instability in passivation performance under operating electric fields.

Downstream Failure Propagation

Failures in the BKPAS module propagate electrically and mechanically. Electrically, inadequate surface passivation causes permanent dark current degradation that cannot be remediated by downstream processing. Structurally, delamination or poor adhesion at the passivation interface can propagate into overlying optical layers, leading to film peeling or pattern distortion.

The fixed charge characteristics of the passivation stack also interact with photodiode doping profiles. If the passivation fixed charge is of incorrect polarity or insufficient magnitude, it can alter the surface electric field, degrading short-wavelength sensitivity and dark current performance.

Thermal Stability Concerns

The passivation stack must maintain its electrical characteristics through all downstream thermal steps. Fixed charges in high-k dielectrics can drift or anneal during subsequent processing, and hydrogen passivation can be lost if hydrogen is driven out of the interface. The integration sequence must account for the cumulative thermal budget to ensure final device parameters are met.

Walk the Real Module

The physical process sequence for the 40nm BSI CIS BKPAS module executes a structured series of deposition, lithography, etch, and curing steps:

1. Oxide hard mask deposition: A protective oxide layer is deposited on the thinned backside silicon surface to serve as an etch mask and structural barrier.
2. Pre Litho Cleaning: Chemical surface cleaning prepares the wafer for photoresist coating by removing particulate and organic residues.
3. Backside Passivation IIP - Photo: Photolithography patterns the photoresist to define regions for backside passivation ion implantation.
4. Back Passivation IIP: Ion implantation introduces dopants at the backside surface to tailor surface electrical potential and assist carrier pinning.
5. Ashing & Strip/Clean: Plasma ashing and wet cleans remove patterned photoresist and post-implant residues.
6. Oxide hard mask etch: Anisotropic etching opens windows in the oxide hard mask layer according to the defined pattern.
7. Vacuum Bake: Thermal processing under vacuum outgasses moisture and volatile contaminants prior to high-vacuum passivation deposition.
8. Rapid Thermal Processing: Short-duration thermal annealing repairs implant lattice damage and activates implanted dopants.
9. RF Plasma: RF plasma treatment conditions the exposed surface, removing residual oxide and controlling surface termination before dielectric deposition.
10. HKD/AR1 AlO deposition: Atomic layer deposition coats an aluminum oxide (Al₂O₃) high-k dielectric layer, providing negative fixed charge for field-effect passivation and anti-reflective properties.
11. HKD/AR2 TaO deposition: A second high-k dielectric layer, such as tantalum oxide (Ta₂O₅), is deposited to tune the refractive index stack and complete the primary passivation layer.
12. BPMD SiO Deposition: A silicon dioxide capping dielectric is deposited by CVD to seal the high-k stack and provide a mechanical buffer for downstream processing.

You can Open BKPAS Step 298 in the interactive flow to inspect this module in the 40nm BSI CIS flow.

Related Learning Paths

Engineers analyzing the 40nm BSI CIS BKPAS module should review these connected integration topics:

• The 40nm BSI CMOS Image Sensor process flow outlines the total integration architecture across frontside and backside processing.
• The 40nm BSI CMOS Image Sensor backside wafer thinning process flow defines the upstream surface preparation and silicon quality entering BKPAS.
• The 40nm BSI CMOS Image Sensor backside substrate-contact integration process flow addresses downstream electrical contacts penetrating the backside dielectric stack.

Future Outlook

Emerging trends in BSI CIS backside passivation focus on multi-component high-k stacks designed to decouple chemical and field-effect passivation. By grading film stoichiometry, researchers aim to maintain high fixed charge density while suppressing interfacial trap generation.

In-situ surface preparation prior to dielectric deposition is also advancing, utilizing atomic-scale plasma or chemical pre-treatments to minimize plasma-induced damage during PEALD. As pixel pitch scales and 3D stacking integration expands, backside passivation stacks must simultaneously deliver optical anti-reflection, electrical surface pinning, and structural reliability across reduced thermal budgets.