Role in the Complete Flow
In a 40nm backside-illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) fabrication sequence, the backside substrate-contact integration module — commonly referred to as the SBST_CONT module — occupies a pivotal position between backside substrate thinning/planarization and backside metallization . The module receives a wafer whose active photodiode array has already been formed on the front side, whose original growth substrate has been mechanically and chemically thinned to a controlled residual thickness, and whose backside surface has been prepared through passivation and surface treatment steps . What this module must deliver downstream is a set of electrically functional, physically robust contacts that connect the thinned backside silicon to the backside interconnect stack, enabling substrate biasing, dark-current suppression, and in some architectures direct power delivery .
The 40nm BSI CIS platform relies on pinned photodiodes (PPD) as the primary photosensitive element . These photodiodes require a well-controlled substrate potential to pin the surface Fermi level and suppress dark current originating from interfacial generation-recombination centers . Without a reliable backside substrate contact, the substrate floating potential drifts, the PPD charge transfer efficiency degrades, and image lag increases . Therefore, the SBST_CONT module is not merely an ohmic contact formation step — it is a device-physics-critical integration point that directly governs quantum efficiency, dark current, and dynamic range .
From a process-flow perspective, the backside substrate-contact integration sits after the 40nm BSI CMOS Image Sensor backside passivation integration process flow has established a surface passivation layer on the thinned backside silicon . It must deliver a clean, low-resistance contact interface before subsequent backside metal deposition and patterning steps can proceed . The contact formation quality at this stage propagates forward into every downstream electrical characterization and reliability test .
Process checkpoint
Where this article enters the flow
Pre Litho Cleaning
In the 40nm BSI CMOS Image Sensor, “40nm BSI CMOS Image Sensor backside substrate-contact integration process flow” leads to this point: Step 310 in the SBST_CONT module.
Open this step to see its rationale, risks, and 2.5D cross-section evolution in the full process flow.
Entry State and Sequence Logic
Upstream Dependencies
When the SBST_CONT module process flow begins, the wafer has traversed several critical upstream modules (Engineering Practice). The frontside device fabrication — including PPD formation, transfer gate, reset gate, and multilevel metallization — is complete . The wafer has been bonded to a handle or carrier wafer, inverted, and the original growth substrate has been thinned through a combination of mechanical grinding and selective chemical etching, stopping on an engineered etch-stop layer . Following thinning, a backside passivation layer has been deposited to suppress surface dark current and provide a controlled interface state density .
The entry surface condition is paramount (Engineering Practice). Native oxide regrowth, organic residues from bonding or handling, and airborne molecular contamination (AMC) accumulated during wafer transport in front-opening unified pods (FOUPs) all conspire to degrade contact quality . The Pre Litho Cleaning integration principles demand that any surface entering a lithography step must be free of particulate and chemical contamination at levels that would distort photoresist adhesion or induce patterning defects . This cleaning requirement is doubly critical here because the same surface will subsequently receive metal deposition for contact formation .
Sequence Ordering Logic
The SBST_CONT module process flow follows a tightly coupled sequence: surface cleaning, lithographic patterning of contact openings, etch of the passivation/dielectric stack to expose the underlying silicon, Pre Litho Cleaning of the post-etch surface, silicide or barrier metal deposition, and thermal annealing to form the contact . The ordering is dictated by several physical constraints:
1 (Engineering Practice). Cleaning before lithography — any particulate or chemical residue on the surface will cause photoresist adhesion failures or induce critical dimension (CD) variation in the contact openings . 2. Lithography before etch — the contact hole positions are defined by photolithographic patterning; misalignment or CD variation here directly translates into contact resistance variation . 3. Post-etch cleaning before metal deposition — the etch process leaves polymer residues and damaged silicon at the contact bottom; these must be removed before silicide formation or metal barrier deposition . 4. Silicide formation controlled by surface preparation — the phase and quality of any silicide formed at the contact interface depend critically on the cleanliness and chemical state of the exposed silicon surface .
This sequence logic ensures that each step receives a surface state compatible with its physical and chemical requirements, and that no step introduces damage that cannot be recovered downstream (Engineering Practice).
Physical and Chemical Mechanisms
Surface Cleaning and Oxide Removal
The fundamental challenge in backside substrate-contact formation is achieving an atomically clean silicon surface at the bottom of a contact hole etched through a dielectric stack . Native silicon dioxide (SiO₂) regrows on any exposed silicon surface upon contact with ambient atmosphere or residual moisture in process environments . This oxide layer, even when only a few atomic layers thick, acts as a tunneling barrier that increases contact resistance and can prevent reliable silicide nucleation .
Two complementary cleaning mechanisms are employed (Engineering Practice). The first is physical bombardment using inert gas (typically argon) plasma, which sputters away organic residues and partially removes native oxide through ion-impact momentum transfer . However, pure physical sputtering introduces lattice damage in the silicon substrate — particularly in n-type silicon — creating deep-level defects that degrade Schottky barrier characteristics and increase contact resistance . The second mechanism is selective chemical etching using remote-plasma-generated reactive fluorine species . In the Siconi™ approach, ammonium fluoride (NH₄F)-based reactive species react selectively with SiO₂ to form volatile or sublimable salts such as ammonium hexafluorosilicate ((NH₄)₂SiF₆), which are subsequently removed by sublimation under controlled thermal conditions . This chemical pathway removes oxide without bombarding the silicon lattice, preserving surface crystallinity .
The combination of physical and chemical cleaning exploits their complementary strengths: Ar plasma handles organic contamination and rough oxide, while the selective chemical etch removes residual native oxide with minimal substrate damage . The physics underlying this selectivity lies in the higher reactivity of SiO₂ with fluorine-containing species compared to crystalline silicon, combined with the reduced ion energy characteristic of remote plasma configurations .
Contact Formation and Silicide Physics
Once the silicon surface is exposed and clean, the contact must be formed . In 40nm BSI CIS, a silicide-last integration scheme is commonly employed, where a titanium (Ti) layer with a titanium nitride (TiN) barrier is deposited, followed by thermal annealing to form titanium silicide (TiSiₓ) at the contact bottom . The silicide formation is governed by solid-state reaction kinetics: titanium atoms diffuse into silicon at elevated temperature, reacting to form a metallic silicide phase with low Schottky barrier height and low specific contact resistivity .
The Schottky barrier height at a metal-silicon interface is fundamentally determined by the interfacial chemical state, the metal work function, and the silicon doping concentration . Any residual oxide or contamination at the interface creates a local barrier that increases the effective contact resistance . This is why the pre-clean sequence is so critical: it directly controls the interfacial chemical state, which in turn governs the silicide phase nucleation and the final Schottky barrier height .
For the 40nm BSI CIS platform, the contact must achieve both low resistance and high reliability under operating conditions that include thermal cycling, bias stress, and prolonged illumination . The silicide phase stability under these conditions depends on the initial formation quality, which is ultimately traceable to the pre-clean step .
Substrate Biasing and Device Physics
The backside substrate contact serves a device-physics function beyond simple ohmic contact . In a BSI CIS, the thinned silicon substrate is the entry path for photons reaching the PPD array . The substrate contact establishes the backside potential that influences the electric field distribution throughout the photodiode depletion region . A well-designed contact ensures that the substrate potential is firmly pinned, creating a stable electric field that:
- Directs photogenerated electrons toward the PPD storage region
- Suppresses electron diffusion into the substrate bulk (reducing crosstalk)
- Minimizes dark current generation at the backside surface
The pinned photodiode structure relies on a heavily doped p+ surface layer to pin the Fermi level at the Si-SiO₂ interface, suppressing dark current from interface states . The backside substrate contact must be compatible with this pinning — it must not introduce carriers or defects that would disturb the pinned potential . A poorly formed contact with high resistance or unstable silicide phases can create local potential fluctuations that propagate through the substrate, degrading dark current uniformity across the pixel array .
Interfaces and Failure Propagation
Upward Tradeoffs: Cleaning Damage vs [P1]. Contact Resistance
The SBST_CONT module sits at a tradeoff crossroads (Engineering Practice). Aggressive physical cleaning (higher Ar plasma intensity) removes more oxide and organic residue but introduces more lattice damage in silicon, which degrades silicide nucleation and increases contact resistance . Conversely, gentle chemical-only cleaning preserves the lattice but may leave insufficient oxide removal in high-aspect-ratio contact holes, also degrading contact resistance . The optimal operating point balances these opposing effects (Engineering Practice).
When the pre-clean is insufficient, native oxide residue remains at the contact bottom . During subsequent thermal annealing, this oxide inhibits uniform silicide formation, resulting in mixed-phase or incomplete silicide regions . These defective interfaces exhibit higher and more variable contact resistance, directly degrading the substrate biasing effectiveness and increasing dark current non-uniformity across the pixel array .
Downward Consequences: Yield and Reliability
Contact resistance variation propagates into yield loss through several mechanisms . If substrate contacts exhibit high resistance, the substrate potential floats, and the PPD charge transfer becomes incomplete, causing image lag — a visible artifact where residual charge from one frame persists into the next . Furthermore, variable substrate potential across the array creates pixel-to-pixel dark current variation, observable as fixed-pattern noise .
Reliability failures also originate from this module (Engineering Practice). Incomplete silicide formation or interfacial contamination can create localized hot spots under bias stress, leading to time-dependent dielectric breakdown or silicide degradation . AMC residues — particularly corrosive species such as hydrogen fluoride (HF) trapped in FOUPs during wafer transport — can react with exposed silicon or metal surfaces between process steps, introducing contamination that is not removed by standard cleans . This contamination may not be immediately detectable but manifests as latent reliability failures during device operation .
Lateral Interfaces: Passivation and Metallization
The contact module interfaces laterally with the backside passivation layer, which must be patterned to open contact windows without damaging the surrounding passivation . Over-etching during contact hole formation can damage the passivation layer, degrading its dark-current suppression function . Under-etching leaves residual dielectric at the contact bottom, blocking silicide formation . The etch selectivity between the dielectric stack and the underlying silicon is therefore a critical parameter — it must be high enough to preserve the silicon surface while completely clearing the dielectric .
On the downstream side, the contact module interfaces with backside metallization . The silicide contact surface must be smooth, clean, and phase-uniform to ensure reliable adhesion and low interface resistance with the subsequently deposited metal layers . Any roughness or contamination at this interface introduces additional series resistance and potential delamination sites .
Walk the Real Module
The detailed step-by-step process flow for the 40nm BSI CMOS Image Sensor backside substrate-contact integration can be explored in the interactive process flow environment . To examine the exact sequence of operations — including the Pre Litho Cleaning step, lithography, etch, post-etch clean, and metal deposition — Open SBST_CONT Step 310 in the interactive flow .
This interactive resource allows engineers and students to trace each step in context, understanding how the entry state, processing operations, and exit conditions chain together to form a complete module (Engineering Practice). The flow is situated within the broader 40nm BSI CMOS Image Sensor process flow, which provides the end-to-end integration context from frontside device fabrication through backside thinning, passivation, contact formation, and final metallization .
Interfaces with Adjacent Modules
The SBST_CONT module does not exist in isolation (Engineering Practice). Its upstream neighbor — the backside passivation module — establishes the surface chemical state and dark-current suppression that the contact module must preserve . The 40nm BSI CMOS Image Sensor backside passivation integration process flow defines the dielectric stack through which contact holes must be etched, and the surface passivation quality that must be maintained around each contact opening .
Downstream, the contact module feeds into backside metal interconnect formation . The contact surface quality directly determines the interface resistance and adhesion reliability of the backside metal stack . In architectures employing backside power delivery — analogous to the selective deep recess source/drain structures described for logic devices — the substrate contact may also serve as a power rail connection, further elevating its resistance and reliability requirements.
Laterally, the contact module must be compatible with the 40nm BSI CMOS Image Sensor light-shield and aperture-grid integration process flow, which defines the optical isolation structures that prevent stray light from reaching non-target pixels . The metal deposits formed during contact creation must not interfere with the light-shield geometry or create reflective surfaces that compromise optical crosstalk performance .
Related Learning Paths
Proximity Gettering and Defect Engineering
Understanding substrate contact quality requires appreciation of the silicon defect landscape . Hydrocarbon molecular ion implantation for proximity gettering creates buried defect sinks that trap metallic impurities (Fe, Cu, Ni, W) and oxygen, preventing them from diffusing to the active device region . These gettering centers must remain compatible with the backside contact formation thermal budget — excessive annealing during silicide formation can destabilize gettering sites and release trapped impurities, degrading dark current and white spot defect density . Engineers studying the SBST_CONT module should therefore also examine gettering integration principles to understand the thermal budget constraints that govern contact anneal conditions .
Contamination Control and Wafer Transport
The AMC management principles demonstrated for 300mm power device production lines apply directly to 40nm BSI CIS fabrication. Between the post-etch clean and metal deposition steps, the wafer spends time in a FOUP, where adsorbed contaminants can desorb from pod walls and recontaminate the freshly cleaned contact surface . Understanding FOUP contamination dynamics — including the effects of dwell time, pod history, and ambient conditions — is essential for maintaining the surface cleanliness that the SBST_CONT module requires . Engineers should study the wafer carrier contamination monitoring literature to appreciate how cross-module contamination control strategies protect contact integrity .
Advanced Cleaning and Surface Preparation
The halogen-sublimation dry pre-clean approach described for germanium oxide removal illustrates the broader family of selective chemical surface preparation techniques. While the 40nm BSI CIS platform primarily employs the Ar/Siconi™ combined clean for silicon surfaces , the underlying principle — using selective chemical reactions to remove oxides while preserving the substrate lattice — is transferable across material systems. Engineers interested in the SBST_CONT module should explore adjacent cleaning technologies to build a comprehensive understanding of surface preparation physics (Engineering Practice).
Future Outlook
The 40nm BSI CIS platform continues to evolve, and the backside substrate-contact integration module faces several emerging challenges and research directions .
3D stacking and hybrid bonding are reshaping the substrate-contact landscape . As die-to-wafer hybrid bonding becomes more prevalent for BSI imagers , the substrate contact must be formed on individually bonded dies rather than full wafers, introducing new uniformity and process-window challenges. The total thickness variation (TTV) across bonded dies directly affects contact depth uniformity, and the protective layers used during backside thinning must be compatible with subsequent contact formation steps .
Backside power delivery is an emerging architecture where substrate contacts serve double duty as both biasing contacts and power rails . This demands lower contact resistance and higher current-carrying capacity, pushing the silicide formation and pre-clean requirements to more aggressive process windows . The deep-recess source/drain concept, while developed for logic transistors, illustrates the direction in which backside contact engineering is evolving — toward larger contact areas and shorter current paths .
Reduced thermal budgets driven by 3D stacking constraints limit the annealing temperatures available for silicide formation . This favors lower-temperature silicide phases and places even greater emphasis on surface preparation quality, since a clean surface can form good silicide at lower temperatures while a contaminated surface cannot . Proximity gettering structures must also be designed to remain stable under these reduced thermal budgets.
Advanced cleaning chemistries continue to be developed (Engineering Practice). The combination of physical and selective chemical cleaning represents the current state of the art, but future generations may employ novel reactive species, in-situ monitoring, or plasma-free approaches to achieve even higher selectivity and lower damage. The integration of cleaning steps with lithography — the Pre Litho Cleaning integration principles that ensure pattern fidelity — will become increasingly critical as contact CD dimensions continue to scale .
References
- Additional Siconi™ pre-clean for reliable TiSix contacts in advanced imager technologies (2019)
- A Review of the Pinned Photodiode for CCD and CMOS Image Sensors (2014)
- Experimental Wafer Carrier Contamination Analysis and Monitoring in Fully Automated 300 mm Power Production Lines (2021)
- A Review of Proximity Gettering Technology for CMOS Image Sensors Using Hydrocarbon Molecular Ion Implantation (2019)
- Silicon VLSI Technology (2000)
- Protocol for thinning the rear substrate of individual chips attached by hybrid bonding of die-to-wafer type (2023, US-2025194268-A1)
- Selective deep recess source/drain structure for direct backside power rail contact (2023, US-2025212513-A1)
- Germanium oxide pre-clean module and process (2014, US-2016192502-A1)