40nm BSI CMOS Image Sensor Light-Shield and Aperture-Grid Integration: Process Flow Principles and Integration Logic

Role in the Complete Flow

In a 40nm backside-illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) process flow, the light-shield (LS) and aperture-grid integration module occupies a critical transitional position between the frontside metallization stack and the backside optical layers [P2]. Its upstream interface receives a partially completed interconnect structure that includes metal routing, via contacts, and dielectric isolation layers — the so-called frontside "wiring" that connects photodiode nodes to peripheral readout circuitry [T1]. The downstream deliverable is a patterned optical barrier layer — typically incorporating a titanium nitride (TiN) barrier or similar refractory metallic compound — that defines the aperture grid through which backside-incident photons are selectively guided toward pinned photodiode (PPD) active regions while stray light is blocked from reaching sensitive pixel boundaries [P3].

The fundamental purpose of this module is to suppress optical crosstalk between adjacent pixels in the BSI CIS array [P4]. In a BSI architecture, light enters from the thinned backside of the silicon substrate, passing through color filters and microlenses before reaching the photodiode junction [P3]. Without an effective light shield and aperture grid, oblique-angle photons or laterally scattered light could traverse inter-pixel gaps and be collected by neighboring photodiodes, degrading modulation transfer function (MTF) and color mixing performance [P4]. The LS_GRID module process flow thus serves as the primary optical isolation mechanism at the metal-grid level, ensuring that the fill-factor advantage of BSI is not undermined by inter-pixel photon leakage [A1].

From a process-flow perspective, this module must deliver: (1) a conformal barrier deposition that fills gaps and lines trench sidewalls with sufficient step coverage, (2) a patterned grid structure with well-defined aperture openings aligned to the underlying photodiode centers, and (3) a chemically and mechanically stable interface that survives subsequent chemical-mechanical planarization (CMP), backside thinning, and thermal treatments without delamination or contamination [P2]. The TiN barrier layer also serves a secondary function as a diffusion barrier, preventing metal species from migrating into the silicon active region during downstream high-temperature steps [P1].

Entry State and Sequence Logic

Upstream Dependencies

The LS_GRID module enters the process flow after the completion of the lower-metal-level interconnect structure and the associated dielectric planarization steps [A2]. In the 40nm BSI CIS process flow, this means the wafer has already undergone transistor formation, photodiode implantation and activation, and multiple levels of metal routing with interlevel dielectric (ILD) deposition and CMP [T2]. The entry surface must be planarized to a controlled topography because the subsequent barrier deposition and grid patterning are highly sensitive to underlying step heights — any residual topography from upstream metal levels will propagate into the aperture grid definition and cause non-uniform aperture dimensions across the pixel array [A2].

A critical sequence dependency involves the silicide contact formation in the pixel and peripheral regions [P1]. As described in the literature, advanced imager technologies employ a silicide-last integration scheme where TiSix contacts are formed by annealing a Ti/TiN stack, and the pre-clean sequence preceding this deposition directly affects contact resistance and yield [P1]. The light-shield and aperture-grid barrier deposition must be sequenced either before or after this silicide module, depending on the integration scheme, because the TiN barrier layer used for the light shield may share process chemistry with the TiN capping layer used in contact formation [P1]. Misalignment in the sequence can lead to unintended interfacial reactions or contamination of the silicide contact interface [P1].

Downstream Consequences

After the LS_GRID module is completed, the wafer proceeds to upper optical clear-layer deposition, color filter array formation, microlens shaping, and ultimately backside substrate thinning — the defining step that converts a frontside-processed wafer into a BSI CIS device [A1]. The aperture grid must remain dimensionally stable through all of these downstream steps (Engineering Practice). Any grid deformation, lateral etch, or delamination during backside thinning or subsequent thermal cycling will directly alter the optical aperture profile and, consequently, the per-pixel quantum efficiency and crosstalk characteristics [P3].

The sequence logic also dictates that the light-shield grid must be compatible with the backside thinning process [A1]. In die-to-wafer hybrid bonding schemes used for advanced BSI CIS, the backside substrate is thinned through a combination of mechanical grinding and selective wet etching to an etch-stop layer [A1]. The light-shield metal stack, being located on the frontside of the bonded pair, must not be exposed to or damaged by the backside thinning chemistries — a requirement that influences the choice of barrier materials and the encapsulation strategy in the LS_GRID module design [A1].

Physical and Chemical Mechanisms

LS/Aperture Grid Barrier Deposition Integration Principles

The core physical mechanism governing the light-shield and aperture-grid barrier deposition is the conformal coating of a high-density metallic or ceramic thin film across a patterned dielectric topology [A2]. The barrier layer — most commonly TiN deposited by atomic layer deposition (ALD) or a combination of physical vapor deposition (PVD) and ALD — must achieve gap-filling capability in narrow inter-pixel trenches while maintaining a planar top surface suitable for subsequent patterning [T1].

The integration logic is grounded in the optical absorption properties of the barrier material [P2]. TiN exhibits broadband optical absorption due to its interband transitions and free-carrier absorption, making it effective at blocking visible and near-infrared photons across the spectral range relevant to CMOS image sensors [T1]. The barrier thickness must be sufficient to attenuate transmitted light to negligible levels — a relationship governed by the Beer-Lambert absorption law, where transmission decreases exponentially with barrier thickness [P4]. However, increasing barrier thickness also increases mechanical stress and raises the risk of delamination, creating a fundamental tradeoff between optical shielding effectiveness and structural reliability (Engineering Practice).

Chemical Reaction Principles in Barrier Deposition

In ALD-based TiN deposition, the growth mechanism relies on self-limiting surface chemical reactions between alternating pulses of a titanium precursor (such as TiCl₄ or an organometallic Ti compound) and a nitrogen source (such as NH₃ or plasma-activated nitrogen species) [P1]. Each reaction cycle deposits a sub-monolayer of TiN, and the cumulative thickness is controlled by the number of cycles [T2]. The self-limiting nature of ALD ensures conformal step coverage even in high-aspect-ratio trench structures, which is essential for the aperture-grid geometry where trench sidewalls must be uniformly coated [P4].

The chemical mechanism involves ligand exchange reactions: the titanium precursor chemisorbs onto hydroxyl-terminated or nitrogen-terminated surfaces, releasing volatile byproducts, and the subsequent nitrogen pulse removes remaining ligands and forms Ti–N bonds [P1]. The process temperature influences both the reaction kinetics and the film composition — higher temperatures promote more complete ligand removal and lower impurity content, but may exceed the thermal budget constraints of underlying layers [T2].

Device Physics Reasoning

From a device physics standpoint, the aperture grid serves two simultaneous functions: optical and electrical [T1]. Optically, it defines the per-pixel light-collection aperture, controlling the angular acceptance and spatial selectivity of photon entry into each photodiode [P2]. The grid opening diameter relative to the pixel pitch determines the effective fill factor — the ratio of light-sensitive area to total pixel area — which directly impacts quantum efficiency [P2]. A narrow aperture improves crosstalk suppression but reduces fill factor; a wide aperture maximizes photon collection but increases the risk of inter-pixel optical leakage [P3].

Electrically, the TiN barrier layer in the grid structure can act as a capacitive coupling element between adjacent pixel nodes if it is not properly grounded or isolated [A2]. The grid metal, being in proximity to the floating diffusion (FD) nodes and transfer gate structures, introduces parasitic capacitance that affects the conversion gain of the pixel [P2]. The integration principle therefore requires that the grid metal be either electrically floated in a controlled manner or tied to a fixed potential (typically ground) to prevent signal-dependent capacitive coupling [A2]. This electrical consideration influences the grid layout design and the connection strategy to the pixel ground network [A2].

Interfaces and Failure Propagation

Upward Interface: Metal Routing to Light Shield

The interface between the underlying metal routing levels and the light-shield grid is mediated by the interlevel dielectric [A2]. The primary failure mode at this interface is topography-induced grid non-uniformity: if the ILD surface retains residual step features from underlying metal lines, the subsequently deposited barrier layer will exhibit thickness variations that translate into aperture-size variations after patterning [A2]. This is a directional tradeoff — tighter planarization requirements upstream reduce grid variability but increase CMP process complexity and cost [A2].

A second failure mode involves metal contamination migration (Engineering Practice). If the light-shield barrier deposition occurs at elevated temperatures, metallic species from underlying metal lines (particularly copper or aluminum used in the interconnect stack) can diffuse upward through grain boundaries or interface defects in the ILD, contaminating the photodiode region and increasing dark current [P1]. The TiN barrier layer is specifically chosen for its effectiveness as a diffusion barrier, but its integrity depends on deposition quality and the absence of pinholes or microcracks [P1].

Downward Interface: Light Shield to Optical Layers

The interface between the completed light-shield grid and the subsequently deposited optical clear layers and color filter array is critical for optical performance [A2]. If the grid surface is not planarized or if the grid sidewalls are not vertical, the color filter material may exhibit non-uniform thickness near aperture edges, causing color-dependent sensitivity variations [P3]. Additionally, any residual metallic particles or sidewall roughness on the grid structure can scatter light into unintended directions, degrading the point-spread function of the pixel [P4].

Failure Propagation to Device Performance

Failures in the LS_GRID module propagate to device-level metrics through several well-defined pathways (Engineering Practice). Aperture-size variation directly translates to per-pixel sensitivity non-uniformity (fixed pattern noise) (Engineering Practice). Grid sidewall roughness or slope causes angular-dependent crosstalk, where the severity of inter-pixel leakage varies with the angle of incident light [P2]. Barrier delamination or cracking, if it occurs during backside thinning or thermal cycling, can expose underlying dielectric layers to wet-etch chemistries, leading to localized etch damage and catastrophic pixel failure [A1].

The most insidious failure mode is latent grid degradation: a barrier layer that appears intact after the LS_GRID module but develops microcracks or interfacial delamination during subsequent high-temperature steps or mechanical stress from wafer bonding and thinning [A1]. Such latent failures may not be detectable at the module level but manifest as elevated dark current or pixel-level sensitivity drift in final device testing, making root-cause identification extremely difficult [P1].

Walk the Real Module

To fully understand the 40nm BSI CIS light-shield and aperture-grid integration in practice, engineers should examine the actual process-step sequence in the interactive flow [P4]. The LS_GRID module process flow involves multiple sub-steps including barrier deposition, grid lithography, pattern transfer etch, and post-etch cleaning — each with specific integration dependencies that must be satisfied in the correct order [A1].

You can Open LS_GRID Step 318 in the interactive flow to explore the actual module sequence, including the barrier deposition and aperture-grid definition steps within the 40nm BSI CMOS image sensor process flow [A1].

The interactive flow also connects to the broader 40nm BSI CMOS Image Sensor process flow, providing context for how the LS_GRID module fits within the complete fabrication sequence [P2]. Engineers studying this module should also reference the 40nm BSI CMOS Image Sensor lower optical clear-layer integration process flow to understand the immediate downstream interface, and the 40nm BSI CMOS Image Sensor backside substrate-contact integration process flow for the backside thinning sequence that the light-shield grid must survive [P2].

Related Learning Paths

Engineers and students interested in the LS_GRID module should explore several adjacent topics within the 40nm BSI CIS process architecture:

1 (Engineering Practice). Pinned Photodiode Physics and Integration — Understanding the PPD structure is essential because the aperture grid is designed to serve the photodiode's optical collection requirements [P3]. The PPD's surface pinning mechanism, doping profile, and charge transfer characteristics directly dictate the optimal aperture geometry [P3].

2. BSI Substrate Thinning and Hybrid Bonding — The light-shield grid must survive the aggressive backside thinning process, making knowledge of the thinning sequence and etch-stop mechanisms critical for grid material selection and encapsulation design [A1].

3. Silicide Contact Integration in Imager Technologies — The TiN barrier layer used in the light-shield grid shares material science and deposition principles with the TiN capping layer in TiSix contact formation [P1]. Understanding the pre-clean and deposition chemistry of contact barriers provides transferable knowledge to grid barrier optimization [P1].

4. Wide-Spectrum CIS Process Design — For applications requiring extended spectral response (UV through near-infrared), the aperture grid design must accommodate the broader angular and wavelength distribution of incident photons, adding complexity to grid optimization [P2].

5. SPAD Integration in Advanced CIS Nodes — The 40nm BSI CIS platform also supports single-photon avalanche diode (SPAD) fabrication, where the light-shield and aperture-grid principles are extended to include optical isolation for Geiger-mode pixel operation [P4].

Future Outlook

The evolution of the LS_GRID module in 40nm BSI CIS and beyond is driven by several converging trends (Engineering Practice). First, the continued shrink of pixel pitch toward sub-micron dimensions demands aperture grids with ever-narrower openings and taller aspect ratios, pushing ALD barrier deposition to its conformality limits and requiring new gap-fill strategies such as flowable CVD or multi-step deposition-etch-deposition sequences [A2].

Second, the adoption of three-dimensional stacked CIS architectures — where the photodiode layer and the readout circuit layer are fabricated on separate wafers and bonded via hybrid bonding — fundamentally changes the role of the light-shield grid [P2]. In stacked architectures, the grid may be positioned between the bonded layers rather than on the frontside, requiring new alignment and integration strategies [A1]. The grid must also serve as a bonding-interface-compatible structure, adding mechanical and chemical compatibility constraints (Engineering Practice).

Third, emerging applications such as SPAD-based LiDAR and time-of-flight sensing in the 40nm BSI CIS platform require the aperture grid to support not only conventional intensity imaging but also single-photon timing performance [P4]. The grid material and geometry must minimize photon timing jitter caused by lateral optical scattering, adding a temporal-resolution dimension to the traditional crosstalk-fill-factor tradeoff [P4]. These emerging requirements are driving research into alternative barrier materials with higher optical density and lower surface roughness, as well as novel grid architectures such as tapered apertures and metasurface-enhanced light-guiding structures [P4].