Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
40nm BSI CMOS Image Sensor Backside Substrate-Contact Integration Process Flow: Principles, Mechanisms, and Module Dependencies
Role in the Complete Flow In a 40nm backside-illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) fabrication sequence, the backside…
40nm BSI CMOS Image Sensor Shallow Trench Isolation Process Flow: Integration Logic, Mechanisms, and Engineering Tradeoffs
Role in the Complete Flow In a 40nm backside illumination (BSI) complementary metal-oxide semiconductor (CMOS) image sensor, the shallow trench isolation (STI) module serves as…
40nm BSI CMOS Image Sensor Sidewall Spacer Integration: Process Flow Principles and Device Physics
Role in the Complete Flow The sidewall spacer (SWS) module in a 40nm back-side illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor occupies a pivotal…
40nm BSI CMOS Image Sensor Backside Wafer Thinning Process Flow: Integration Principles and Physical Mechanisms
Role in the Complete Flow The 40nm BSI CMOS Image Sensor represents a generation of imaging devices where the photodiode array and the readout circuitry occupy opposite faces of…
40nm BSI CMOS Image Sensor Starting Wafer and Substrate Preparation: Principles, Integration Logic, and Process Physics
Role in the Complete Flow The 40nm BSI CMOS Image Sensor starting wafer and substrate preparation module — often referred to as the WFR module — is the foundational process…
7nm FinFET Process Flow: Integration Principles, Device Physics, and Module Dependencies
Process Map and Scope The 7nm FinFET technology node represents a pivotal generation in advanced logic semiconductor manufacturing, where three-dimensional channel wrapping…
7nm FinFET Dummy-Poly Opening and Planarization Process Flow: Integration Principles, Physical Mechanisms, and Module Dependencies
Role in the Complete Flow The 7nm FinFET dummy-poly opening and planarization (POP) module sits at a pivotal junction in the replacement metal gate (RMG) integration scheme…
7nm FinFET Pad Oxidation Pre-Clean: Integration Principles and Surface Physics
Role in the Complete Flow In a 7nm FinFET process flow, the pre-pad oxidation surface cleaning operation sits at the critical boundary between incoming substrate preparation and…
7nm FinFET Starting Wafer and Substrate Preparation: Integration Principles, Device Physics, and Process Flow
Role in the Complete Flow The starting wafer and substrate preparation (WFR) module is the foundational entry point of the entire 7nm FinFET process flow.
Understanding Damage in Semiconductor Manufacturing: Physical Mechanisms, Process Interactions, and Advanced Node Challenges
Manufacturing damage can affect crystal, interfaces, and films through different mechanisms. The linked flow shows relevant steps but does not measure their damage or prove a complete repair cycle.
Defect in Semiconductor Manufacturing: Physical Origins, Electrical Impact, and Scaling Challenges
In semiconductor manufacturing, a defect is any deviation from the ideal atomic arrangement, geometric pattern, or electrical behavior of a device structure that degrades…
Fin Height Adjustment in Semiconductor Manufacturing: Physical Principles, Process Mechanisms, and Advanced Node Integration
Fin height adjustment is a critical semiconductor process step that controls the vertical dimension of silicon fins in Fin Field-Effect Transistor (FinFET) devices.