Fin Height Adjustment in Semiconductor Manufacturing: Physical Principles, Process Mechanisms, and Advanced Node Integration

Introduction

Fin height adjustment is a critical semiconductor process step that controls the vertical dimension of silicon fins in Fin Field-Effect Transistor (FinFET) devices [P3]. After initial fin patterning, the fin height must be precisely set to achieve desired device performance characteristics, including drive current, electrostatic control, and leakage suppression [P3]. In FinFET architectures, the fin sidewalls serve as the active channel surfaces, meaning that fin height directly determines the effective channel width and thus the current-driving capability of the device [P3].

Two principal integration approaches exist for defining fin height (Engineering Practice). In the silicon-on-insulator (SOI) scheme, the fin etch stops on the buried oxide (BOX) layer, and the fin height is determined by the SOI layer thickness [P1]. In the bulk silicon approach, fins are etched deeply into the substrate and subsequently isolated by oxide deposition, followed by a recess etch to expose the active fin surfaces [P1]. Regardless of the integration scheme, achieving precise and uniform fin height is essential for device performance consistency and yield [P3].

The importance of fin height adjustment has grown with each technology node advancement (Engineering Practice). As transistors transitioned from planar architectures to three-dimensional (3D) structures, the fin height became a first-order parameter affecting device electrostatics, parasitic capacitances, and source/drain (S/D) engineering [P1]. Moreover, fin height control interacts with numerous downstream process steps, including gate formation, S/D epitaxial growth, and isolation engineering [A1]. Understanding the underlying physical mechanisms and process interactions is therefore essential for any semiconductor engineer working at advanced nodes [T1].

Physics & Mechanism

Fin Formation and Height Definition

The physical mechanism of fin height adjustment depends fundamentally on the substrate type and integration scheme chosen [A1]. In SOI-based FinFETs, the fin height is physically defined by the thickness of the silicon layer above the BOX, and the fin patterning etch terminates on the oxide layer, providing a natural etch stop [P1]. The fin height is thus predetermined by the substrate specification rather than adjusted post-patterning [P3]. In contrast, bulk silicon FinFETs require a more complex sequence: fins are etched deeply into the silicon substrate, an oxide dielectric is deposited to fill the gaps between fins, and the oxide is subsequently recessed to expose the desired fin height [P1][P4].

The recess of the isolation oxide to expose the fin sidewalls is the core of fin height adjustment in bulk substrates [A3]. This step, often referred to as fin etch-back or oxide recess, relies on the etch selectivity between the oxide isolation material and the silicon fin [T1]. The etch must remove oxide preferentially while minimizing silicon recess — the unintended removal of silicon from the fin sidewalls and top surface [P4]. The physical principle governing this selectivity lies in the different volatilities of etch byproducts: fluorine-based plasmas form volatile silicon fluorides and silicon oxide fluorides, but the reaction rates and desorption characteristics differ between materials, enabling preferential oxide removal [P4].

Chemical Reaction Principles

The chemical mechanisms underlying fin recess involve plasma-generated radicals and ions interacting with the dielectric and semiconductor surfaces [A3]. In a fluorine-based plasma, atomic fluorine radicals react with silicon dioxide to form volatile SiF₄ and other fluorinated products, while ion bombardment enhances the reaction rate at horizontal surfaces [T1][P4]. The synergy between chemical radicals and ion bombardment is described by Langmuir–Hinshelwood-type surface kinetics, where the etch rate depends on both the adsorption coverage of reactive species and the ion-enhanced reaction at the surface [P4].

For the fin sidewalls, which are exposed to the plasma during the recess step, the primary concern is silicon recess — the unwanted etching of the crystalline silicon channel [A3]. Silicon etching in fluorine plasmas proceeds through the formation of volatile silicon fluorides, but the reaction can be suppressed through sidewall passivation [T1]. Inhibitor species, such as fluorocarbon polymers or oxyfluoride byproducts, can deposit on vertical surfaces and protect them from spontaneous chemical etching, allowing the etch to proceed preferentially in the vertical direction [T1][P4]. The balance between passivation and etching is controlled by the plasma chemistry, ion energy, and substrate temperature [P4].

For III-V channel materials such as InGaAs, different etch chemistries are required [P2]. BCl₃/SiCl₄/Ar plasmas form volatile chlorides with In, Ga, and As species, achieving high selectivity and directionality for fin patterning [P2]. Subsequent digital etching cycles of oxidation and oxide removal provide sub-nanometer control of fin dimensions and sidewall smoothness, complementing the initial fin recess [P2].

Device Physics Rationale

From a device physics perspective, fin height is a first-order parameter because it directly determines the effective channel width of a FinFET [P3]. Each fin contributes two sidewall channels (and potentially a top channel in tri-gate configurations), so the total drive current scales with fin height [P3]. A taller fin provides more channel area and higher drive current but also increases parasitic capacitance and makes the device more susceptible to structural instabilities [A1]. Conversely, a shorter fin reduces drive current but improves electrostatic integrity by reducing the fringing field components that weaken gate control [P3].

The fin height also affects the short-channel behavior [P3]. In a double-gate or tri-gate FinFET, the gate modulates the channel potential from multiple sides, and the effectiveness of this modulation depends on the fin geometry [P3]. The natural length — a characteristic dimension governing short-channel effects — scales with the fin width and gate oxide thickness, but fin height influences the fringing field patterns and the subthreshold swing [P3]. Therefore, fin height adjustment is not merely a dimensional control exercise but a device physics optimization that balances drive current, leakage, and electrostatic control [P3].

Process Principles

Etch Chemistry and Directionality

The choice of etch chemistry is the primary lever for controlling the fin recess process [A3]. Fluorine-based plasmas are commonly used for oxide recess due to their ability to form volatile products with both silicon and silicon dioxide [T1]. The directionality of the etch — the ratio of vertical to lateral etch rates — is controlled by the balance between ion-enhanced etching and spontaneous chemical etching [P4]. Increasing the ion energy component enhances vertical etching, producing more anisotropic profiles, while a higher radical flux contribution increases isotropic etching, which can lead to lateral silicon recess [T1][P4].

Gas chemistry composition directly affects sidewall passivation [A1]. Adding polymer-forming gases increases the deposition of inhibitory films on vertical surfaces, suppressing lateral etching and protecting fin sidewalls [T1]. However, excessive polymer formation can lead to non-vertical sidewall profiles and incomplete oxide removal in the fin trenches [T1]. The etchant chemistry must be tuned to achieve a balance where the oxide is efficiently removed from the recess areas while the silicon fins remain protected [A3]. This principle of balancing chemical and physical etch components through gas chemistry composition is a fundamental concept in critical dimension trim processes as well [T1].

Ion Energy and Plasma Parameters

The ion energy, controlled by the plasma source power and bias voltage, directly influences the etch anisotropy and the potential for silicon damage [P4]. Higher ion energies enhance the vertical etch rate and improve directionality but also increase the risk of physical sputtering of the silicon fins [P4]. The sheath electric field in the plasma determines the ion energy and angular distribution, and thus the degree of anisotropy achievable [P4]. Lower pressures generally produce more directional ion flux due to fewer collisions in the sheath, improving profile control [P4].

Substrate temperature also plays a critical role (Engineering Practice). Lower substrate temperatures can suppress spontaneous chemical etching by reducing the thermal desorption of etch products, effectively increasing anisotropy [P4]. In deep reactive ion etching (DRIE) processes, substrate cooling is used to promote the formation of passivating films on sidewalls, which protects against lateral etching while allowing vertical etching to proceed under ion bombardment [P4].

Selectivity and Silicon Recess Control

The selectivity between the oxide isolation material and the silicon fin is a fundamental parameter for fin height adjustment [A1]. High selectivity ensures that once the oxide is recessed to the target level, the silicon fin is not significantly etched, preserving the fin height and sidewall quality [P1]. In practice, some degree of silicon recess is often unavoidable, and the process must be designed to minimize it [P4]. The selectivity depends on the plasma chemistry, ion energy, and the specific materials involved [T1].

For advanced nodes using III-V channel materials, the fin etch and subsequent digital etching processes use different chemistries — for example, inductively coupled plasma (ICP) etching with BCl₃/SiCl₄/Ar achieves high aspect-ratio, smooth sidewall fin structures, and digital etching further reduces fin width and improves sidewall quality [P2]. The number of digital etch cycles directly determines the final fin width and sidewall quality, thereby affecting electrostatic control and device performance uniformity [P2].

Wall Fin and Isolation Height Control

In advanced FinFET integration schemes, dielectric wall fin structures are introduced between adjacent semiconductor fins to provide physical and electrical isolation [A1]. The height of these wall fin structures is controlled through a multilayer dielectric deposition and selective recess etch process, where etch selectivity between different dielectric materials enables precise height control [A2]. By adjusting the wall fin height, the effective fin sidewall height — and consequently the volume of the S/D epitaxial layer — can be controlled [A1][A3]. If the wall fin height is insufficient, adjacent S/D epitaxial layers may merge, causing electrical shorts; if excessive, the S/D epitaxial volume is reduced, degrading device performance [A1].

Challenges & Failure Modes

Silicon Recess and Sidewall Damage

One of the most significant challenges in fin height adjustment is silicon recess — the unintended etching of the fin material during the oxide recess step [P4]. Silicon recess reduces the effective fin height, degrading drive current and altering the device electrostatics [P3]. The physical mechanism involves both chemical etching by fluorine radicals reacting with silicon and physical sputtering by energetic ions [T1][P4]. The extent of silicon recess is influenced by the etch selectivity, the over-etch time required to clear all oxide from the fin gaps, and the uniformity of the oxide thickness [P1].

Surface roughness generated during the fin recess is another critical concern (Engineering Practice). Because the fin sidewalls serve as the active channel interface, roughness induced by the etch process can create interface traps and degrade carrier mobility [P4]. The roughness originates from the stochastic nature of ion bombardment and chemical reactions at the atomic scale, and is exacerbated by non-uniform passivation [P4]. Post-etch surface treatments, such as wet chemical smoothing or thermal oxidation and stripping, are often needed to restore surface quality [P4].

Fin Height Uniformity

Achieving uniform fin height across the wafer and across different device patterns is a persistent challenge [A1]. The fin recess depth depends on local pattern density, as closely spaced fins create micro-loading effects where the etch rate varies with feature spacing [P1]. In areas with high fin density, the reduced gas transport into narrow trenches can slow the oxide etch rate, leading to less recess and taller effective fins compared to isolated regions [A3]. This non-uniformity translates to device-to-device variations in drive current and threshold voltage, affecting circuit performance and yield [P1].

Aspect-ratio-dependent etching (ARDE) is a related phenomenon where the etch rate depends on the trench aspect ratio (Engineering Practice). As fins become taller and spacing narrower at advanced nodes, ARDE effects become more pronounced, making fin height uniformity increasingly difficult to achieve [P1][P4]. The charging effect — where ions are deflected by charge accumulation on insulating surfaces — further complicates etch uniformity in high-aspect-ratio structures [P1].

Wall Fin Structure Integrity

In integration schemes using dielectric wall fins, additional failure modes arise [A1]. Over-etching of the dielectric layers during wall fin recess can reduce the wall fin height below the desired level, compromising isolation between adjacent S/D regions [A2]. Conversely, inadequate etch selectivity between the dielectric materials can leave residual material on the wall fin, affecting the subsequent S/D epitaxial growth [A2]. Interface defects between different dielectric layers in the wall fin, caused by differences in thermal expansion coefficients or chemical incompatibility, can introduce stress concentration points and delamination risks [A2].

The bending or deformation of the recessed third dielectric layer in the wall fin structure is another failure mode [A3]. If this layer extends too far above the isolation insulating layer, it may bend, compromising the structural integrity and the intended isolation function [A3]. Precise control of the interface height between the dielectric layers is therefore essential, requiring tight control of the etch selectivity and process uniformity [A3].

Metrology Limitations

Measuring fin height and recess depth presents its own set of challenges, particularly at advanced nodes [P1]. Critical dimension (CD) metrology techniques face fundamental physical limits as device dimensions shrink [P1]. CD-SEM (Critical Dimension Scanning Electron Microscopy) relies on electron-material scattering to generate morphology contrast, but charging effects and shadowing in 3D structures can distort measurements [P1]. Optical critical dimension (OCD) scatterometry uses light diffraction and interference from periodic structures to invert for average CD and profiles, but becomes increasingly model-dependent as structures become more complex [P1]. No single metrology technique meets all application needs at advanced nodes, necessitating complementary techniques and hybrid metrology approaches [P1].

Technology Node Evolution

From Planar to FinFET (28 nm and Beyond)

The transition from planar MOSFETs to FinFETs was driven by the fundamental limitations of planar device scaling [P3]. As gate lengths shrank toward the sub-20 nm regime, planar devices suffered severe short-channel effects, requiring heavy channel doping that degraded carrier mobility and increased junction leakage [P3]. The FinFET architecture, first proposed as a self-aligned double-gate MOSFET, addressed these limitations by using the vertical fin sidewalls as channel surfaces, with the gate wrapping around the fin to control the channel from multiple sides [P3]. Early FinFET demonstrations showed that double-gate structures could suppress short-channel effects without increasing channel doping, maintaining good threshold voltage and subthreshold characteristics at ultra-short gate lengths [P3].

14 nm Node: Mainstream FinFET

By the 14 nm node, FinFETs had become the mainstream transistor architecture, and fin height adjustment processes had matured significantly [P4]. The bulk silicon approach became dominant, as it offered cost advantages over SOI substrates while still enabling 3D transistor formation [T1]. The fin recess process — involving oxide deposition for shallow trench isolation (STI) followed by selective oxide etch-back — became a critical step in the 14nm FinFET integration flow [P1]. The plasma etching community developed specialized chemistries and process sequences to achieve the selectivity and profile control needed for fin recess at these dimensions [P4].

The two-step etch approach described in the literature — first creating a vertical profile for the fins, followed by a tapered profile for the isolation trenches — exemplified the process sophistication achieved at this node [P4]. The oxide etch-back to expose the fins required precise endpoint control and selectivity to avoid silicon recess [P1]. At this node, fin patterning increasingly relied on self-aligned double patterning techniques to achieve the tight pitch requirements [P1].

7 nm and Beyond

At the 7 nm node and beyond, fin height adjustment faces even greater challenges [P1]. The fins must be taller and narrower, increasing the aspect ratio and exacerbating ARDE and charging effects [P1]. The 7nm FinFET process flow requires atomic-level control of fin dimensions, prompting the adoption of digital etching techniques that use self-limiting oxidation-deoxidation cycles for sub-nanometer material removal [P2]. These techniques, originally developed for III-V fin processing, complement traditional plasma etch-back by providing a smoothing and fine-tuning capability [P2].

Metrology requirements have also evolved significantly (Engineering Practice). The 22 nm node marked a major shift from planar to 3D transistor architectures, posing entirely new metrology requirements including height, sidewall angle, roughness, and profile morphology measurements [P1]. Traditional techniques such as CD-SEM and OCD scatterometry begin to approach their physical limits beyond the 22 nm node, necessitating hybrid metrology approaches [P1]. Additionally, source drain recess processes at these nodes must be carefully coordinated with fin height to ensure proper S/D epitaxial volume [A1].

The evolution toward nanowire and nanosheet architectures represents the next frontier, where the fin concept itself is transformed into suspended channel structures [P3]. This transition will require new approaches to height and dimension control, building on the principles developed for FinFET fin height adjustment [P1][P3].

Related Processes

Fin height adjustment does not occur in isolation but is deeply interconnected with numerous adjacent process steps [A3]. The initial fin patterning — involving lithography, hard mask definition, and plasma etching — defines the fin width and pitch, which directly influence the subsequent recess process [P1]. The fin patterning etch must create vertical sidewalls that will later serve as channel surfaces, and any sidewall angle or roughness introduced at this step will be inherited and potentially amplified during fin recess [P4].

The S/D recess step, which selectively removes silicon from the S/D regions to create recesses for epitaxial growth, shares process physics with fin recess — both rely on selective etching of silicon relative to dielectric materials [A1]. The S/D epitaxial growth that follows is directly affected by the fin height, as the exposed fin sidewall area determines the nucleation surface area and the growth volume [A1][A2]. If the fin height is not properly controlled, the epitaxial layers may merge between adjacent fins, causing shorts [A1].

Gate formation — whether gate-first or gate-last (replacement metal gate, RMG) — is also influenced by fin height [A2]. The gate wraps around the fin, and the fin height determines the gate-channel overlap area [P3]. Chemical mechanical polishing (CMP) steps used in gate-last integration to planarize the gate material must account for the fin height, as the gate height over the fin after CMP is a critical parameter [P1]. The interlayer dielectric (ILD) deposition and CMP that follow gate formation are similarly affected by the topography established by the fin height [A2].

Future Outlook

The future of fin height adjustment is shaped by the continuing evolution of transistor architectures and the push toward atomic-scale process control [P3]. As the industry moves toward gate-all-around (GAA) nanosheet and nanowire devices, the concept of fin height will be replaced by channel sheet or wire dimension control, but the underlying principles of selective etching and recess control will remain relevant [P1][P3].

Atomic layer etching (ALE) is emerging as a key technology for achieving the precision required at advanced nodes [P4]. By using self-limiting surface reactions — analogous to atomic layer deposition (ALD) but in reverse — ALE can remove material with atomic-layer precision, dramatically improving the control of fin recess and silicon recess [P2]. The digital etching approach demonstrated for III-V fin processing, with its oxidation-deoxidation cycles, represents an early implementation of this concept [P2].

Hybrid metrology, combining multiple measurement techniques with computational fusion, will be essential for process control at future nodes [P1]. The integration of CD-SEM, OCD, critical dimension small-angle X-ray scattering (CD-SAXS), and other emerging techniques will enable the multi-parameter measurement capability needed to control fin height, sidewall angle, roughness, and profile simultaneously [P1]. The development of new etch chemistries and process sequences for emerging channel materials — including III-V compounds, 2D materials, and engineered substrates — will continue to drive innovation in fin height adjustment processes [P2]. The fundamental physics of plasma-surface interactions, selectivity control, and surface quality preservation will remain the foundation upon which these advances are built [P4].