7nm FinFET Dummy-Poly Opening and Planarization Process Flow: Integration Principles, Physical Mechanisms, and Module Dependencies

Role in the Complete Flow

The 7nm FinFET dummy-poly opening and planarization (POP) module sits at a pivotal junction in the replacement metal gate (RMG) integration scheme, bridging front-end transistor formation with the gate stack replacement that defines final device characteristics [P1]. Upstream, this module receives a fully formed dummy-gate stack—comprising a dummy dielectric, amorphous-silicon (a-Si) or polysilicon dummy gate electrode, and hard-mask layers—embedded within a dielectric stack of contact-etch-stop-layer (CESL) and inter-layer dielectric level-zero (ILD0) that has been deposited over source/drain (S/D) epitaxial regions, spacers, and fins [P1]. The dummy-gate structures serve as placeholders that define the geometric footprint and vertical height of the eventual metal gates, while protecting the fin channel regions during all upstream S/D and spacer processing [P2].

Downstream, the POP module must deliver a cleanly opened recess at every gate site, exposing the fin top and sidewalls with minimal residual material, minimal ILD0 loss, and a highly planar topography that sets the stage for interfacial layer regrowth, high-k dielectric atomic layer deposition (ALD), and metal gate fill [P1]. Because the 7nm FinFET node demands tight gate-height uniformity across the wafer—gate height directly governs parasitic gate resistance and overlap capacitance—the CMP planarization step that precedes dummy-poly removal effectively defines the first-order gate-height budget for the entire RMG flow [P1]. Any non-uniformity introduced here propagates irreversibly into threshold-voltage variability, drive-current mismatch, and reliability degradation in the finished device [P1].

The CESL deposition integration principles are central to this module's role: the CESL acts as both an etch-stop boundary during dummy-poly removal and as a stress-transmission medium that couples S/D strain into the channel [A1]. The CESL must remain intact and planar after the POP sequence so that subsequent RMG steps can proceed without exposing or damaging S/D silicide regions that are formed later through vias opened in the CESL+ILD0 stack [P1].

Entry State and Sequence Logic

Upstream Dependencies

At the entry to the POP module, the 7nm FinFET structure has already undergone fin patterning via self-aligned double or quadruple patterning (SADP/SAQP), shallow trench isolation (STI) formation, well doping, dummy-gate stack deposition and patterning, spacer formation, epitaxial S/D formation, and CESL+ILD0 deposition [P2][P3]. The CESL deposition integration principles dictate that this layer conformally encapsulates the S/D epi, spacers, and dummy-gate hard masks, providing a continuous etch-stop surface [A1]. The ILD0 is then deposited over the CESL and planarized by chemical mechanical planarization (CMP) to establish a flat top surface that roughly coincides with the top of the dummy-gate hard mask [A1][P1].

The sequence logic demands that the ILD0 CMP step—sometimes called the "pre-POP planarization"—be completed before dummy-poly opening, because this CMP sets the initial gate-height reference (Engineering Practice). In 7nm FinFET flows, an additional CMP step may be included to planarize the dummy a-Si gate prior to gate patterning, easing the lithographic burden of printing gate features over the three-dimensional fin topology [P1]. This means the POP module enters with a structure whose topography has already been globally flattened, but whose dummy-gate recess still contains the full dummy stack (Engineering Practice).

Downstream Handoff

Once the dummy-poly opening and planarization sequence is complete, the wafer is handed off to the dummy-dielectric removal step, which strips the sacrificial oxide or nitride from the fin surface using diluted hydrofluoric acid (HF) or dry chemical clean [P1]. This is immediately followed by interfacial-layer (IL) oxidation, high-k dielectric ALD, and metal-gate deposition [P1]. The quality of the POP handoff—measured by recess depth uniformity, sidewall profile, and ILD0 dishing—directly controls the high-k and metal-gate conformality in the high-aspect-ratio gate trenches, which in turn governs equivalent oxide thickness (EOT), gate leakage, and effective work function (EWF) stability [P1].

The 7nm FinFET process flow provides the broader integration context in which this module operates, and the 7nm FinFET replacement metal gate integration process flow details the immediate downstream consumer of the POP output [P1].

Physical and Chemical Mechanisms

CMP Planarization Mechanism

The planarization step that opens the dummy-poly surface relies on the synergistic action of mechanical abrasion and chemical dissolution [A1]. A rotating polishing pad and slurry containing abrasive particles and reactive chemistry selectively remove the ILD0 oxide from the top of the dummy-gate stack while being halted or slowed by the harder dummy-gate hard-mask or dummy-poly material beneath [T1]. The chemical component of the slurry softens or dissolves the oxide surface, while the mechanical component shears away the reaction products, exposing fresh material for continued removal [T1]. The selectivity between ILD0 oxide and the dummy-gate hard mask is the primary control variable: higher selectivity yields a sharper planarization stop with minimal dummy-poly loss, while lower selectivity risks eroding the dummy gate before all ILD0 is cleared [A1].

The physical basis for planarity lies in the differential removal rate between high and low regions: protruding features experience greater pad pressure and higher removal rates, causing the surface to converge toward flatness over the polishing cycle [T3]. However, pattern-density variation across the die—dense gate arrays versus isolated gates—introduces localized dishing and erosion, which are the dominant sources of gate-height non-uniformity in 7nm FinFET POP [T3].

Dummy-Poly Removal Mechanism

After CMP exposes the dummy-poly electrode, the dummy-poly opening step employs anisotropic dry etch processes that selectively remove the polysilicon or a-Si material at a faster rate than the surrounding ILD0 and CESL [A1]. The etch chemistry is chosen to exploit the chemical-etch-rate difference between silicon-based gate materials and silicon-oxide or silicon-nitride dielectrics, so that the dielectric sidewalls act as self-aligned etch masks defining the gate trench [T1]. The anisotropic nature of the plasma etch—driven by vertical ion bombardment—ensures that the recess is formed predominantly in the vertical direction, preserving the lateral dimension of the gate footprint [T3].

The dummy dielectric beneath the dummy poly is then removed by wet or dry etch, typically using diluted HF or a vapor-phase etchant, which dissolves the sacrificial oxide or nitride while leaving the fin silicon surface ready for interfacial-layer regrowth [P1]. The chemical principle here is selective dissolution: the etchant attacks Si–O or Si–N bonds in the dummy dielectric at a rate far exceeding that of the crystalline silicon fin, thereby exposing the channel without etching into it [T1].

CESL Deposition Integration Principles

The CESL is deposited conformally over the S/D epi, spacers, and dummy-gate structures before ILD0 fill, serving multiple physical functions simultaneously [A1]. Mechanically, it provides a compliant stress-transfer medium: the CESL material's intrinsic stress (tensile or compressive) couples strain from the S/D epi into the fin channel, modifying the band structure and carrier effective mass [P2]. Chemically, the CESL acts as an etch-stop during the POP etch sequence because its nitride or oxynitride composition is far more resistant to the oxide-selective etchants used for ILD0 and dummy-dielectric removal [A1]. During CMP, the CESL provides a mechanical boundary that prevents the polishing from descending into the S/D regions if the ILD0 is over-polished [A1].

At the 7nm FinFET node, the CESL deposition integration principles become especially critical because the fin geometry creates complex three-dimensional stress fields that depend on fin width, fin height, and gate pitch [P3]. The CESL must maintain uniform thickness and composition across these features to ensure consistent strain delivery and etch-stop performance [P1].

Interfaces and Failure Propagation

ILD0-to-Dummy-Gate Interface

The interface between the ILD0 oxide and the dummy-gate hard mask is the primary CMP stopping boundary [P1]. If the CMP planarization fails to fully clear the ILD0 from the dummy-gate top, residual oxide patches will block subsequent dummy-poly etch, leaving incomplete gate recesses that result in metal-gate discontinuity and catastrophic device failure [A1]. Conversely, if the CMP over-polishes, it erodes the dummy-gate hard mask and potentially the dummy poly, reducing the gate-height budget and causing non-uniform recess depths across the wafer [P1]. This directly impacts gate resistance and parasitic capacitance in the finished RMG stack [P1].

Dummy-Poly-to-Fin Interface

The interface between the dummy poly and the dummy dielectric (and ultimately the fin surface) is where etch selectivity and residue control become paramount [A1]. Incomplete dummy-poly removal leaves silicon residues in the gate trench, which contaminate the high-k/metal-gate stack and cause threshold-voltage shifts and gate-leakage degradation [T1]. Aggressive over-etch, while ensuring complete removal, risks lateral etching of the dummy dielectric and exposes the fin sidewalls to plasma damage, increasing interface-trap density and degrading carrier mobility [P1]. The $\text{SF}_6$ plasma treatment described in the literature exemplifies a post-etch remedy: fluorine atoms passivate Si–O and Hf–O bonds, reducing interface-trap density and partially recovering mobility lost to fin sidewall orientation and etch damage [P1].

CESL-to-ILD0 Interface

The CESL-to-ILD0 interface must withstand the entire POP etch sequence without degradation [A2]. If the CESL is compromised—through CMP erosion, plasma damage, or chemical attack—it loses its etch-stop function, allowing subsequent etchants to reach the S/D epi regions [A1]. This results in S/D leakage current increase and parasitic capacitance growth between gate and S/D, both of which degrade Ion/Ioff ratios and switching performance [P2]. The 7nm FinFET source-drain integration process flow discusses how S/D epi quality and CESL integrity are co-optimized [P3].

Pattern-Density-Driven Dishing

Pattern-density variation across the die is a fundamental failure-propagation pathway in POP CMP [P3]. Dense gate arrays experience higher localized removal rates than isolated gates due to pad pressure distribution differences, causing ILD0 dishing in dense regions and residual ILD0 in sparse regions [T3]. This translates to gate-height variation across the chip, which in turn causes threshold-voltage mismatch, drive-current variation, and BTI reliability scatter [P1]. At the 7nm FinFET node, where gate-pitch scaling places gates in extremely close proximity, the dishing penalty is amplified unless CMP pad conditioning, slurry chemistry, and polishing time are carefully co-optimized [T3].

Downstream Consequences for RMG

Any non-uniformity introduced during POP propagates irreversibly into the RMG module (Engineering Practice). Gate-height variation causes metal-gate fill non-uniformity, which alters parasitic gate resistance and gate-to-S/D overlap capacitance [P1]. Residual dummy-poly material causes EOT thickening and gate-leakage degradation in the affected gates [P1]. CESL damage causes S/D-to-gate leakage pathways that cannot be repaired in downstream steps [A1]. These failure modes are the primary reason why the POP module is considered a yield-critical step in 7nm FinFET manufacturing [P1].

Walk the Real Module

To see the exact sequence of operations, layer transitions, and step-level dependencies in the POP module, you can explore the interactive process flow (Engineering Practice). The module's critical operations—from CESL and ILD0 deposition through CMP planarization to dummy-poly etch and recess formation—are captured step-by-step, allowing you to trace how each operation modifies the device cross-section and feeds the next step [P3].

The key step where dummy-poly opening and planarization converge is captured at Open POP Step 155 in the interactive flow (Engineering Practice). At this step, the planarized ILD0 surface exposes the dummy-gate hard mask, initiating the dummy-poly removal sequence that creates the recesses for subsequent high-k and metal-gate deposition [A1]. Examining this step in context reveals how the upstream S/D and spacer modules define the boundary conditions for the POP etch, and how the downstream RMG module consumes the recess geometry produced here [P1].

The broader 7nm FinFET process flow article contextualizes this step within the complete integration scheme, while the 7nm FinFET replacement metal gate integration process flow article details how the opened recesses are filled with high-k dielectric and metal-gate materials [P1].

Related Learning Paths

Engineers studying the POP module should explore adjacent process clusters to build a complete mental model of 7nm FinFET integration:

• Upstream: S/D and Spacer Integration — The 7nm FinFET source-drain integration process flow explains how epitaxial S/D formation and spacer definition create the boundary conditions that the POP module must respect [P3]. The CESL deposition that follows S/D processing is the same CESL that serves as the etch-stop in POP, so understanding its stress and etch properties in the S/D context is essential [A1].

• Downstream: RMG Integration — The 7nm FinFET replacement metal gate integration process flow details the high-k dielectric deposition, EWF engineering, and metal-gate fill steps that consume the recesses created by POP [P1]. The gate-height budget set by POP CMP directly controls the metal-gate fill aspect ratio and the final gate resistance [P1].

• Foundational: Complete Flow Architecture — The 7nm FinFET process flow article provides the module dependency map that situates POP within the full front-end-of-line (FEOL) sequence, from fin patterning through BEOL interconnect [P3].

• Physical Foundations: Device Scaling — Understanding why the POP module must achieve such tight uniformity at 7nm requires grounding in FinFET device physics, including electrostatic control, short-channel effect suppression, and the trade-off between Ion and Ioff as dimensions scale [T2][P2]. The subthreshold current relationship $I_{ds} \propto \exp(qV_{gs}/\eta kT)$ and the subthreshold swing limit $S = \eta \frac{kT}{q} \ln(10)$ define the fundamental constraint that makes gate-height and EOT uniformity so critical at this node [T2].

• CMP Fundamentals: Planarization Physics — The CMP planarization physics discussed in the device fabrication literature provides the theoretical basis for understanding pattern-density effects, selectivity, and dishing in the POP context [T3]. The same principles apply to STI CMP and W-plug CMP, making this a transferable knowledge domain (Engineering Practice).

Future Outlook

As FinFET scaling extends toward 5nm and 3nm nodes and transitions to gate-all-around (GAA) nanosheet architectures, the dummy-poly opening and planarization module faces several evolutionary pressures [P2]. In GAA devices, the dummy-gate removal must not only create a recess for metal-gate fill but also release the suspended nanosheet channels from their sacrificial layers, adding a lateral etch component to what was previously a purely vertical recess operation [A1]. This increases the complexity of etch selectivity: the etchant must remove the sacrificial layers between nanosheets while preserving the CESL and the inner-spacer dielectrics that maintain channel-to-S/D isolation [A2].

EUV lithography adoption at and below 7nm reduces the multi-patterning complexity that burdens gate-pitch control, but it also tightens the gate-height uniformity requirement because smaller gate pitches amplify the impact of per-gate height variation on parasitic capacitance [P3]. This pushes CMP planarization toward more advanced endpoint-detection and in-situ metrology integration [P3].

Emerging research directions include the development of self-assembled monolayer (SAM) etch-stop materials that can provide atomically sharp CMP stopping boundaries, reducing the hard-mask thickness and freeing gate-height budget for taller metal gates [A1]. Additionally, area-selective ALD of dielectric barrier layers within the opened recesses may reduce the reliance on global CMP selectivity by locally protecting critical interfaces during dummy-poly etch [P1]. These innovations aim to decouple the POP module's etch and planarization functions from the cumulative variability of upstream patterning, enabling tighter gate-height control as the industry moves toward sub-7nm nodes [P3].