Plasma-enhanced deposition methods are favored over purely thermal techniques because they provide conformality over three-dimensional FinFET topography while maintaining a low thermal budget and controllable film density .
In depth
Device Context and Integration Rationale
The CESL deposition step is inserted after source/drain activation anneal and surface clean to form a conformal, chemically robust liner that protects activated junctions and exposed silicon surfaces during subsequent contact a
nd dielectric integration steps . In the MOL contact module of a 7 nm HKMG FinFET flow, this layer establishes a well-defined etch stop and stress liner before the deposition of oxide liners and PMD dielectric fill, ensuring that later aggressive contact etches terminate predictably without encroaching into source/drain or gate-adjacent regions . The positioning of CESL immediately after junction anneal is intentional, because the silicon lattice and dopant profiles are already stabilized, allowing the CESL-induced stress to couple elastically into the channel without being relaxed by later high-temperature steps . This step therefore prepares a mechanically and chemically conditioned surface that is compatible with both the oxide liner deposition and the FCVD-based PMD fill that follow, where etch selectivity and interface integrity become critical .
Physical and Chemical Deposition Mechanism
CESL deposition relies on plasma-enhanced surface reactions in which silicon- and nitrogen-containing precursor fragments are generated in a low-energy plasma and adsorb onto exposed surfaces to form an amorphous hydrogenated silicon nitride network . The plasma dissociation step creates highly reactive radicals that lower the activation energy for film formation, enabling deposition at a thermal budget compatible with post-junction processing and HKMG stacks . As these radicals chemisorb and cross-link, an intrinsically stressed amorphous SixNyHz film forms, whose stress state arises from sub-stoichiometric bonding configurations and hydrogen incorporation within the network . From a device-physics perspective, this intrinsic film stress is transmitted through elastic coupling into the silicon fin and channel region, slightly distorting the crystal lattice and modifying carrier band structure and effective mass, which can enhance mobility without altering electrostatics .
Material, Method Selection, and Parameter Interactions
Silicon nitride is selected for CESL because it simultaneously offers high etch selectivity relative to silicon dioxide, good barrier properties against diffusion of reactive species, and a tunable intrinsic stress that can be leveraged for strain engineering . Plasma-enhanced deposition methods are favored over purely thermal techniques because they provide conformality over three-dimensional FinFET topography while maintaining a low thermal budget and controllable film density . Within this framework, deposition parameters interact directionally: increasing plasma reactivity enhances ligand removal and film densification but also increases the risk of ion-induced damage, while higher precursor availability promotes uniform coverage but can raise hydrogen content and reduce stress stability . Post-deposition treatments further modify bonding configurations by reducing hydrogen content and increasing Si–N network connectivity, which strengthens tensile stress transfer but can relax compressive stress depending on the initial film structure .
Node-Specific Considerations for 7 nm FinFETs
At the 7 nm node, fins exhibit extreme aspect ratios and narrow spacing, making conformal coverage and uniform stress transfer more challenging than in earlier planar technologies . The reduced silicon volume in the fin amplifies the sensitivity of channel strain to liner stress, so small variations in CESL film structure can lead to measurable device variability, linking this step directly to performance uniformity . In addition, tighter contact pitches and more aggressive contact etches increase reliance on the CESL as a precise etch stop and protective barrier, elevating the integration importance of film density and interface adhesion . These scaling-driven constraints explain why CESL deposition at 7 nm must balance mechanical stress engineering with damage minimization and conformality in a way that was less critical at larger nodes .
Risks & Challenges
[High] Plasma-Induced Fin or Gate Damage: Excessive ion energy or directional plasma exposure during deposition can cause physical damage or charge trapping at fin sidewalls and HKMG interfaces, degrading mobility and increasing leakage, consistent with plasma–surface interaction mechanisms described for PEALD and PECVD processes .
[High] Non-Uniform Stress Transfer: Variations in film density or hydrogen content across complex 3D topography can lead to spatially non-uniform intrinsic stress, resulting in uneven strain transmission into the channel and device-to-device performance variability .
[Medium] Poor Etch-Stop Selectivity: Insufficient film densification or improper stoichiometry can reduce etch resistance relative to downstream oxide etches, allowing partial penetration into underlying silicon or isolation regions during contact formation .
[Medium] Stress Relaxation After Deposition: Subsequent thermal or radiation-based treatments can break or reorganize Si–N and Si–H bonds, relaxing the intended stress state and reducing the effectiveness of strain engineering in the channel .
[Low] Interface Adhesion Failure: Contamination or incomplete surface preparation prior to CESL deposition can weaken interfacial bonding, leading to delamination or micro-cracking during later mechanical or thermal loading steps (Engineering Practice).
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