7nm FinFET Replacement Metal Gate Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow

The replacement metal gate (RMG) module in a 7nm FinFET process flow is the defining structural transformation that converts a temporary polysilicon dummy gate into the final high-k/metal gate (HKMG) stack. Upstream, this module receives a fully formed transistor skeleton: fin structures patterned on the substrate, source/drain epitaxial regions grown and doped, dummy poly-Si gates defined and patterned, spacers formed, and interlayer dielectric (ILD) deposited and planarized to expose the dummy gate tops. The 7nm FinFET process flow positions RMG as a mid-to-late-stage module that bridges front-end-of-line (FEOL) transistor formation with middle-of-line (MOL) contact and back-end-of-line (BEOL) interconnect integration.

The fundamental reason RMG exists is thermal budget management. In a gate-first approach, the high-k dielectric and metal gate must survive all subsequent high-temperature steps — including source/drain activation anneals and silicidation — which degrades the high-k/channel interface, increases interface state density, and causes threshold voltage (Vth) shifts. Compared to high-temperature thermal oxidation, dielectric deposition requires a significantly reduced thermal budget, making it the preferred approach during front-end processing when thermal exposure must be restricted [T1]. By deferring the formation of the final gate stack until after all high-temperature processing is complete, the RMG approach preserves the chemical and structural integrity of the high-k dielectric and work function metals. At 7nm FinFET nodes, where equivalent oxide thickness scaling and Vth tuning precision are critical for power-performance tradeoffs, this thermal isolation is a structural necessity.

Downstream, the RMG module must deliver a planarized, electrically functional gate stack whose top surface is coplanar with the surrounding ILD, ready to receive MOL contact formation and subsequent BEOL metal layers. The module must also ensure that the gate fill metal completely fills the narrow gate trenches without voids, and that the work function metal layers provide the correct Vth for both n-type and p-type FinFETs on the same wafer.

Entry State and Sequence Logic

Upstream Dependencies

When the RMG module begins, the 7nm FinFET wafer has already completed the dummy-poly opening and planarization sequence — the preceding module that deposited pre-metal dielectric, performed chemical mechanical polishing (CMP) to expose dummy poly-Si gate tops, and removed the dummy poly to create empty gate trenches. This dummy-poly opening and planarization process is the direct upstream neighbor, and its quality directly constrains RMG: if CMP leaves non-uniform recess heights or if dummy poly removal is incomplete, the RMG module inherits those defects and propagates them into the final gate stack.

The integration logic follows a strict sequential dependency chain. First, dummy gate removal must be selective to the surrounding dielectric and spacer materials, leaving the fin channel surfaces exposed but undamaged. Second, sacrificial protection oxide is deposited to shield exposed sidewalls during dual-oxide lithographic patterning and wet etching operations. In replacement metal gate integration, high-k dielectric and work function metal films are deposited sequentially over the exposed fin channel prior to gap filling and CMP planarization [P4]. Prior to high-k deposition, a thin chemical interfacial oxide layer is formed on the clean silicon channel surface. This ultra-thin chemical oxide layer passivates the semiconductor/dielectric interface, reducing dangling bonds and interface trap density that would otherwise degrade subthreshold swing and increase off-state leakage.

Sequence Within the RMG Module

The RMG module itself follows a tightly sequenced internal flow. After dummy poly removal, a sacrificial protection oxide deposition covers the exposed trench and fin surfaces. Dual-oxide lithographic patterning and selective etching are performed to establish multi-oxide thickness regions across the chip. After removing residual sacrificial oxides and cleaning the channel, wet chemical processing forms a chemical oxide interfacial layer. High-k dielectric (typically HfO₂-based) is then deposited over the chemical oxide layer, followed by post-deposition annealing. Work function metal layers — with tailored compositions for n-type and p-type devices — are deposited and selectively patterned. Finally, a low-resistance gate fill metal (such as tungsten) is deposited to fill the trench. While tungsten is less suitable as a primary work function layer due to its near-midgap work function, its application as a high-conformality fill metal in replacement gate stacks remains highly advantageous [P1]. A final CMP step removes overburden metal and planarizes the gate stack flush with the surrounding dielectric.

Physical and Chemical Mechanisms

Interfacial Chemical Oxide Formation and Channel Passivation

The chemical oxide formation principle rests on the physics of semiconductor-dielectric interface states. At a bare silicon or SiGe surface, dangling bonds create electronic states within the bandgap that act as charge traps. These traps capture and release carriers in a stochastic manner, adding a capacitive component in parallel with the depletion capacitance, which degrades the subthreshold slope and shifts Vth unpredictably. Controlled wet chemical oxidation satisfies surface dangling bonds, creating a stoichiometric, ultra-thin SiO₂ interfacial layer with a well-defined band offset relative to the channel.

This chemical oxide interfacial layer reduces the density of interface states (Dit) to levels compatible with 7nm device requirements. While high-temperature thermal oxidation can produce low trap densities, high thermal processing is precluded in the RMG module because it would damage pre-formed source/drain structures. Wet chemical oxide growth at low temperatures produces a high-quality interface while respecting the strict thermal budget constraints.

High-k Dielectric and Work Function Metal Deposition

After chemical oxide formation, the high-k dielectric is deposited. The physical mechanism enabling high-k materials (with dielectric constants significantly higher than SiO₂) is their polarizability: the higher k allows a physically thicker dielectric layer to achieve the same equivalent oxide thickness, reducing direct tunneling leakage current. At 7nm FinFET nodes, the high-k/channel interface quality established by the underlying chemical oxide layer directly governs the high-k's nucleation density and film morphology, which in turn affects gate leakage and bias temperature instability (BTI) reliability.

Work function metal deposition is governed by Schottky barrier physics: the metal work function relative to the semiconductor electron affinity determines the band alignment and thus the flat-band voltage and Vth. For a 7nm FinFET CMOS process, different work function metals must be deposited for n-type and p-type devices on the same wafer, requiring a multi-mask, multi-deposition sequence with selective etchback steps between them. The work function metal must also act as an oxygen diffusion barrier, preventing the high-k from losing oxygen during subsequent thermal steps and forming oxygen vacancies that act as bulk traps.

Dummy Gate Removal Chemistry

The dummy poly-Si removal step employs wet or dry etching chemistry selective to the surrounding oxide and nitride spacer materials. The mechanism relies on chemical selectivity between polysilicon and dielectric materials: for example, alkaline or fluorine-based chemistries can isotropically remove poly-Si while leaving SiO₂ and Si₃N₄ largely intact. The challenge at 7nm is the high aspect ratio of the gate trench — the etch must remove all poly-Si from the bottom of a narrow, deep trench without laterally attacking the fin or spacer materials, which would enlarge the gate length and degrade short-channel control.

CMP Planarization Physics

The final metal CMP step in RMG relies on the synergistic combination of chemical softening and mechanical abrasion. The slurry chemically modifies the metal surface, forming a softened or hydrated layer that is then mechanically removed by abrasive particles. The Preston equation describes the removal rate as proportional to the applied pressure and relative velocity, but chemical kinetics — governed by Langmuir-Hinshelwood-type adsorption-desorption equilibrium — modulate the effective removal rate. Controlled over-polishing is required to clear metal from the ILD surface, but excessive over-polish can recess the gate metal or expose source/drain regions, causing gate resistance variation and contact failures. The planarization principles governing this step are central to RMG yield.

Interfaces and Failure Propagation

Upstream-to-RMG Interface Failures

The RMG module is particularly sensitive to upstream defects because it operates on already-patterned structures with no opportunity to re-grow or re-clean the channel. If the dummy-poly opening module leaves polymer residue or particles in the gate trench, subsequent chemical oxide growth and high-k deposition will nucleate on contaminated surfaces, creating localized thin spots or pinholes in the interfacial layer. These defects propagate as localized high-leakage paths through the high-k dielectric, manifesting as elevated gate leakage current and potential dielectric breakdown.

Similarly, if the fin sidewall surfaces were damaged during dummy gate etching — for example, by plasma-induced surface roughening or ion bombardment — the increased surface area and crystal damage increase the interface state density, directly degrading subthreshold swing and mobility. This is an irreversible propagation: the RMG module has no mechanism to repair fin sidewall damage, so the defect becomes a permanent device characteristic.

RMG Internal Interface Tradeoffs

Within the RMG module, several directional tradeoffs exist. The chemical interfacial oxide thickness trades off against equivalent oxide thickness: a thicker oxide reduces Dit and improves reliability but increases the effective gate oxide thickness, reducing on-state drive current. The work function metal thickness trades off against gate fill volume: thicker work function layers provide better Vth tuning margin and diffusion barrier performance but reduce the available volume for the low-resistance fill metal, increasing gate resistance and RC delay.

The high-k deposition conformality on the three-dimensional fin geometry is another critical interface. ALD processes provide excellent conformality, but at 7nm fin dimensions with high aspect ratios, precursor penetration and byproduct removal become diffusion-limited, potentially causing thinner high-k at the fin bottom or trench sidewalls. This non-uniformity creates spatially varying gate capacitance, leading to within-die Vth variation and degraded matching characteristics.

Downstream Consequences

Failures in the RMG module propagate downstream. Gate metal CMP non-uniformity — whether within-die or within-wafer — directly causes gate height variation, which propagates into MOL contact formation as varying contact-to-gate spacing and parasitic capacitance. In severe cases, over-polishing can expose raised source/drain epitaxial regions, causing metal shorts between gate and source/drain. Under-polishing leaves metal residue on the ILD surface, creating inter-gate shorts.

Gate fill voids — caused by poor metal conformality in narrow trenches or gas entrapment during deposition — increase gate resistance, which degrades switching speed and can cause electromigration reliability failures under high-frequency AC stress. These failures are often not detected at the RMG module itself but emerge as yield losses during final wafer test.

The threshold voltage control achieved during work function metal deposition is a critical downstream parameter. Vth variation directly affects the Ion/Ioff tradeoff: if Vth is too low, off-state leakage rises exponentially per the subthreshold current equation, increasing static power consumption beyond design limits. If Vth is too high, on-state drive current decreases, degrading circuit speed. Because Vth is set by the work function metal and locked in during RMG, there is no downstream correction mechanism.

Walk the Real Module

To see the exact step-by-step sequence of the 7nm FinFET RMG module — including the interfacial oxide deposition, high-k and work function metal formation, gate fill, and CMP planarization — readers can explore the interactive process flow directly. The module begins at the point where dummy poly has been removed and the gate trench is ready to receive the final gate stack:

Protection Oxide Deposition step in the interactive flow

This interactive tool allows engineers and students to trace each step in context, understanding how physical and chemical mechanisms map to actual process sequence positions within the complete 7nm FinFET flow. By walking through the steps sequentially, one can observe how the upstream dummy-poly opening transitions into the RMG gate stack formation, and how the RMG module hands off to downstream MOL and BEOL modules.

For comparison with earlier technology generations, the 14nm FinFET replacement gate flow also employs RMG but with relaxed dimensional constraints and different work function metal strategies, illustrating how the same integration concept adapts to different nodes.

Related Learning Paths

Engineers studying the 7nm FinFET RMG module should connect to several adjacent topics for a complete understanding:

• The FinFET device physics and process principles provide the foundational understanding of why three-dimensional gate structures require conformal deposition processes.
• The 7nm FinFET contact integration process flow is the immediate downstream module that depends on RMG's planarization quality and gate height uniformity.
• The broader 7nm FinFET process flow article contextualizes RMG within the complete sequence from fin formation through BEOL.

Additionally, understanding NMOS transistor formation provides insight into why the RMG module must support dual work function tuning — different metal stacks for n-type and p-type devices on the same wafer — which is one of the module's most complex integration challenges.

Future Outlook

As scaling continues beyond 7nm toward gate-all-around (GAA) nanosheet and forksheet architectures, the RMG concept evolves. In GAA structures, the replacement gate process must fill around horizontally suspended channels, creating even more challenging deposition and fill requirements. The interfacial oxide layer becomes even more critical because the channel release process exposes inner surfaces that require careful cleaning and passivation.

Research directions include exploring new work function metal systems that can provide finer Vth tuning with thinner layers, enabling more gate fill volume for lower resistance. Novel CMP selectivity enhancement methods offer paths to tighter planarization control without changing slurry chemistry. Additionally, the integration of backside power delivery schemes may restructure the RMG module's downstream interface, decoupling gate formation from frontside interconnect constraints and opening new architectural possibilities.

The core principle — thermally isolating the high-k/metal gate stack from high-temperature source/drain processing — remains valid across advanced node architectures. The RMG module's evolution will continue to be driven by the tension between deposition conformality, interface quality, and narrowing process windows.