An NMOS transistor is a gate-controlled device in which electrons carry current between n-type source and drain regions through a channel in a p-type body. Two different events need separate names: manufacturing creates the body, gate and terminal structures; applying a suitable gate voltage later creates an electron inversion channel during operation. The inversion layer is not a manufacturing step, and an n-well in an n-well CMOS scheme ordinarily serves the neighboring p-channel device rather than defining the NMOS body .
The Device Before It Turns On
The gate and its dielectric sit above a p-type body. N-type source and drain regions flank the area controlled by the gate. With the gate below the needed bias, the surface does not provide the same conductive electron path; a suitable gate bias changes the surface potential and allows electrons to connect the terminals. Threshold voltage depends on the body, gate stack and channel electrostatics, not on a single implant alone . A chip can use a p-type substrate or a dedicated p-well for this body, depending on its CMOS integration.
Process checkpoint
Understand P-Well Ion Implantation in context
Locate the periphery p-well body region before NMOS channel adjustment.
Process context for “NMOS Transistor: Operation and Formation”: 40nm BSI CMOS Image Sensor · WELL · Step 60
- 1. P-Well IIP
- 2. NMOS VT Adjust IIP
- 3. PolySi - Etch
- 4. NMOS LDD IIP
- 5. NMOS S/D, FD IIP
- 6. Dopants Activation
What Fabrication Adds
The site's 40nm BSI CMOS Image Sensor flow offers one planar example, not a universal NMOS recipe. Its periphery P-Well IIP helps establish a p-type body region; NMOS VT Adjust IIP represents channel electrostatic adjustment; PolySi - Etch defines the gate shape; NMOS LDD IIP forms an extension near the gate; NMOS S/D, FD IIP forms deeper n-type terminal regions in this mixed NMOS and image-sensor module; and Dopants Activation treats introduced dopants. The Flow's FD label also covers the sensor's floating-diffusion region, so it must not be read as a generic part of every NMOS transistor. Each named Step has a different purpose, and several intervening Steps in the actual Flow are omitted from this teaching trail.
Why the Sequence Affects Electrical Behavior
Channel adjustment and the gate stack influence turn-on behavior. Extension and deeper source/drain regions affect the current path and drain-side field. Their geometry and doping must be considered with channel behavior rather than treated as independent labels .
After implantation, thermal treatment can repair lattice damage and make more dopants electrically active. It can also redistribute a dopant profile, so activation and junction shape must be evaluated separately on the finished device .
Follow the Learning Route
In the linked Flow, locate the p-well before the threshold-adjust step, then identify the patterned gate, extension and deeper terminal steps. Finally, compare their intended profiles with the activation Step's effect. The Blog is public; the Step explanations follow their account permissions. For focused background, see threshold voltage, ion implantation and source and drain.
References
Modern Semiconductor Devices for Integrated Circuits - MOS Transistor
Chenming Hu
Modern Semiconductor Devices for Integrated Circuits · Ch6 MOS Transistor
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379