7nm FinFETPreview

lithography and wet etch operations in the RMG flow [A1]. After poly open, the fin sidewalls, STI corners, and residual interfacial oxides are highly vulnerable to chemical attack and contamination, which can translate into interface state generation and threshold voltage instability if left unprotected, as interface quality directly controls gate electrostatics in scaled MOSFETs [T1]. The deposited protection oxide therefore serves as a sacrificial and protective dielectric that preserves the integrity of the high‑k/Si interfacial layer and fin geometry until the Dual Gate Oxide lithography and selective removal steps define the final gate dielectric regions [A1]. By positioning this step before DGO lithography and wet etch, the flow ensures that aggressive resist processing, plasma descum, and selective oxide etchants interact with a controllable deposited film rather than the device‑critical interface, reducing variability and reliability risk [A1].

Physical and Chemical Mechanism

The protection oxide is formed by a deposition process in which silicon‑oxygen bonds are created through surface‑limited chemical reactions, analogous to deposited SiO₂ mechanisms described for ALD oxides in high‑k/metal‑gate integration [P1]. Unlike thermal oxidation, which consumes silicon from the channel and fin sidewalls, deposited oxides build up by chemisorption and ligand exchange reactions at the surface, thereby decoupling dielectric formation from substrate consumption [P1]. This distinction is critical in FinFET geometries, where any additional silicon loss would alter fin width and electrostatic control, directly impacting subthreshold slope and short‑channel behavior [T1]. The deposited oxide also modifies surface chemical potential by saturating dangling bonds and hydroxyl‑terminated sites, which reduces the reactivity of the underlying materials during subsequent wet and plasma processes [A1]. In physical terms, the protection oxide acts as a diffusion barrier that lowers the effective flux of reactive species toward the high‑k interface, consistent with Fickian diffusion suppression concepts used in dielectric capping layers for metal‑gate protection [A1].

Material and Method Selection Logic

A deposited silicon oxide is selected for this step because its chemical compatibility with both silicon and high‑k dielectrics minimizes interfacial dipole formation and unintended work‑function shifts, which are known to be sensitive to interface chemistry in RMG processes [P3]. Compared with other oxides, SiO₂ exhibits well‑understood etch selectivity and surface chemistry, enabling it to function as a predictable sacrificial layer during DGO patterning [P1]. Deposition methods that rely on surface‑reaction‑limited kinetics are favored because they provide conformal coverage over three‑dimensional fin sidewalls and STI edges, a requirement that conventional line‑of‑sight techniques cannot meet in advanced FinFET structures [P4]. From a parameter‑interaction perspective, increasing surface reaction completeness improves film density and barrier effectiveness, while excessive energetic activation can introduce defect states or fixed charges that later couple into the gate stack electrostatics [P4]. Thus, the integration logic emphasizes a balance between chemical completeness, conformality, and minimal plasma or thermal damage to the underlying high‑k and channel materials [P1].

7 nm Node–Specific Considerations

At the 7 nm technology node, fin dimensions and gate lengths are sufficiently small that even minor variations in sidewall oxide integrity can translate into measurable threshold voltage variation and reliability degradation, due to the exponential sensitivity of subthreshold current to interface states [T1]. The protection oxide deposition therefore plays a disproportionate role in controlling variability by stabilizing the surface chemistry prior to dual gate oxide definition [A1]. Additionally, the high aspect ratio of 7 nm FinFET gate trenches amplifies the importance of conformal deposition physics, making surface‑limited deposition mechanisms effectively mandatory rather than optional, as emphasized in ALD‑based gate stack integration literature [P4]. In this context, the protection oxide is not merely a temporary film but a critical enabler that allows subsequent selective etch steps to be executed with sufficient process margin at advanced nodes [A1].