7nm FinFET Source-Drain Integration: Process Flow Principles, Device Physics, and Module Dependencies

Role in the Complete Flow

The source-drain (SD) integration module in a 7nm FinFET process occupies a pivotal position between front-end-of-line (FEOL) transistor definition and the replacement metal gate (RMG) sequence that finalizes the gate stack [T3]. When the SD module receives the wafer, the fin structures have already been patterned through self-aligned double/quadruple patterning, shallow trench isolation (STI) has been formed and recessed to expose the active fins, and the dummy gate stack — including the sacrificial gate electrode and gate dielectric layers — has been deposited and patterned over the fins [P1][P2]. The well doping and channel engineering implants that set the threshold voltage baseline are also complete at this entry point [T1].

What the SD module must deliver downstream is a fully formed, strain-engineered, low-resistance source and drain structure that is electrically isolated from the gate by precisely defined spacers, and ready for the subsequent interlayer dielectric zero (ILD0) deposition, chemical mechanical polish (CMP) planarization, and dummy gate removal steps that lead into the high-k and metal-gate (HKMG) replacement sequence [P1][P2]. In other words, the SD module is responsible for converting the patterned transistor skeleton into a functional three-terminal device with properly doped, strain-optimized, and electrically accessible source/drain regions [T1].

At the 7nm node, this responsibility is amplified because parasitic source/drain series resistance and contact-to-gate capacitance have become comparable to — or even larger than — the intrinsic channel resistance and capacitance [P1]. This means the SD module's quality directly governs whether the 7nm FinFET achieves its drive current and leakage targets, making it one of the most performance-critical modules in the entire 7nm FinFET process flow [T3].

Entry State and Sequence Logic

Upstream Dependencies

Before the SD module begins, several upstream modules must deliver their outputs with high fidelity (Engineering Practice). The fin formation module must provide fins with well-controlled critical dimensions and smooth sidewalls, because fin profile variation propagates directly into the epitaxial source/drain growth quality and junction uniformity [P2]. The dummy gate module must have defined the gate length and gate profile accurately, since the gate edges serve as the self-aligned boundary for spacer formation, which in turn defines the source/drain epitaxy window and the extension implant positions [T1].

The sequence logic follows a strict self-alignment principle: the dummy gate is patterned first, then spacers are formed on the gate sidewalls, and only then is the source/drain region opened for epitaxial growth or implantation [T1][P2]. This ordering ensures that the source/drain regions are physically defined by the gate edges plus the spacer width, rather than by independent lithographic patterning, which would introduce unacceptable overlay error at 7nm dimensions [P2].

Downstream Consequences

After the SD module completes, the wafer enters ILD0 deposition and CMP planarization, which must protect the source/drain epi and spacers while providing a flat surface for dummy gate removal [P1][P2]. The RMG module then replaces the sacrificial gate with the high-k dielectric and metal gate stack [P3]. Any defect or dimensional deviation introduced during SD integration — such as spacer width variation, epi faceting irregularities, or silicide formation problems — will propagate into the RMG module and manifest as threshold voltage shifts, parasitic capacitance changes, or contact resistance variability [T2][P3].

Physical and Chemical Mechanisms

Spacer Deposition and Etchback

The spacer formation process is fundamentally a conformal deposition followed by anisotropic etchback [T2]. A dielectric layer — commonly silicon oxycarbonitride (SiOCN) or silicon nitride at advanced nodes — is deposited conformally over the entire topography, including the vertical sidewalls of the dummy gate [T1][A2]. Because the deposition is conformal, the film is thicker along the vertical gate edges than over flat regions [P2]. The subsequent anisotropic plasma etch removes the horizontal film while leaving the vertical portion intact as the sidewall spacer [T1].

The physical principle here is directional ion bombardment in a plasma etch environment: ions accelerated vertically preferentially remove material on horizontal surfaces, while the vertical sidewall film is protected by the angular dependence of ion incidence [T3]. This self-alignment mechanism allows the spacer width to be defined by the deposited film's conformality profile rather than by lithographic printing, which is essential at 7nm where direct patterning of such features is not feasible [P2][T1].

At 7nm, the SiOCN spacer material is chosen because it provides the necessary etching selectivity relative to the surrounding materials, adequate mechanical integrity to withstand subsequent epitaxial growth pressure, and dielectric properties that help manage the gate-to-source/drain parasitic capacitance [A2]. The dielectric constant of the spacer material directly affects the fringing field coupling between the gate and the source/drain regions, which in turn influences short-channel effect suppression and the on/off current ratio [P3].

Selective Epitaxial Source/Drain Growth

The 7nm source-drain integration relies heavily on selective epitaxial growth of doped semiconductor materials in the source/drain openings [T1]. For PMOS devices, silicon-germanium (SiGe) is grown selectively on the exposed silicon fin surfaces, while for NMOS, phosphorus-doped silicon or silicon-phosphorus may be used [P1][P2]. The selectivity is achieved through the chemical principle that epitaxial growth proceeds on crystalline silicon surfaces but is suppressed on dielectric surfaces (oxide, nitride, SiOCN) through the use of chlorinated precursor chemistries that etch non-crystalline deposits preferentially [P1].

The epitaxial layer serves two simultaneous functions (Engineering Practice). First, it provides an in-situ doped source/drain region with high active carrier concentration, reducing the series resistance that has become dominant at 7nm [T2][P1]. Second, because SiGe has a larger lattice constant than silicon, growing a SiGe source/drain region adjacent to the silicon channel induces compressive strain in the channel, which modifies the band structure and increases hole mobility for PMOS devices [P1][P2]. This strain engineering mechanism is a bandstructure modification: the strain alters the valence band degeneracy and the effective mass of holes, leading to higher drive current without requiring further gate length scaling [T3].

Junction Formation and Silicidation

After epitaxial growth, the source/drain regions undergo a thermal treatment to activate the implanted or in-situ doped impurities, driving them into substitutional lattice sites where they act as donors or acceptors [T1]. The physics of doping relies on impurity energy levels that lie near the conduction band (for donors) or valence band (for acceptors), allowing thermal excitation to ionize them at energies far below the bandgap, thereby dramatically increasing free carrier concentration [T1].

Following junction activation, a self-aligned silicide (salicide) process forms a low-resistance metallic interface on the source/drain surfaces [T2]. A metal layer is deposited uniformly, and a thermal reaction causes the metal to react with exposed silicon in the source/drain regions to form silicide, while the metal over dielectric regions (spacer, STI) remains unreacted and is selectively removed [T2]. The silicide reduces the sheet resistance component between the contact and the channel, and its self-alignment to the gate edge is ensured by the spacer, which prevents silicide formation on the gate sidewall [T2][T1].

Interfaces and Failure Propagation

Spacer-to-Epi Interface

The interface between the SiOCN spacer and the epitaxial source/drain region is a critical boundary where several failure modes can originate [P3]. If the spacer etchback is too aggressive, the spacer may be undercut or thinned, allowing the epitaxial growth to encroach laterally toward the gate, which increases gate-to-source/drain capacitance and can cause electrical shorting [T1][P3]. Conversely, if the spacer is too wide, the source/drain extension is pushed away from the channel, increasing the series resistance and degrading drive current [T3].

The directional tradeoff is clear: a narrower spacer improves resistance but worsens capacitance and short-channel immunity, while a wider spacer improves electrostatic control but degrades drive current [P3][T3]. At 7nm, this tradeoff is extremely tight because both the parasitic resistance and capacitance are comparable to the intrinsic channel values, leaving little margin for suboptimal spacer engineering [P1].

Epi-to-Fin Interface

The epitaxial source/drain material must lattice-match to the fin surface to grow defect-free crystal [P3]. If the fin surface is damaged by previous etch steps, or if the exposed fin area is contaminated, the epitaxial growth may nucleate defects, stacking faults, or dislocations that propagate into the channel region and degrade carrier mobility and junction leakage [P2][T2]. The faceting behavior of the epi growth — the tendency of the crystal to grow with specific crystallographic facets — also affects the contact area available for silicidation and subsequent metal contact formation, which in turn determines the contact resistance [T2].

Silicide-to-Contact Interface

The silicide formation consumes silicon from the source/drain region, creating a slightly recessed interface [T2]. If the silicide formation depth is not well controlled, it can consume too much of the shallow source/drain junction, leading to junction leakage or shorting to the underlying substrate [T3]. The silicide phase uniformity also matters: different silicide phases have different resistivities and Schottky barrier heights, which directly affect the contact resistance that is a dominant component of the total source/drain series resistance at 7nm [T2][P1].

Downstream Propagation to RMG

Any spacer width variation or epi profile non-uniformity introduced during SD integration propagates into the RMG module (Engineering Practice). After ILD0 CMP and dummy gate removal, the gate trench is defined by the inner surfaces of the spacers [P3]. If the spacers are asymmetric or vary in width across the wafer, the resulting metal gate will have non-uniform dimensions, causing threshold voltage variability and performance spread [P3][P2]. This makes the SD module not just a performance module but also a variability control module for the downstream gate stack integration [T3].

Walk the Real Module

To see exactly how these principles are applied in a real 7nm FinFET process flow, you can explore the Open SD Step 119 in the interactive flow [P1]. This step represents the source-drain module within the broader 7nm FinFET process flow, and examining it in context reveals how the spacer deposition, epi growth, and junction formation steps are sequenced relative to the dummy gate and the subsequent ILD0 and RMG modules [P1].

For a broader view of how the SD module fits into the complete transistor fabrication sequence, the 7nm FinFET process flow overview article provides the full integration context [P2]. The 7nm FinFET gate stack integration process flow article details what happens downstream after the SD module delivers its outputs [P2]. And for understanding the planarization and dummy gate opening steps that immediately follow SD completion, the 7nm FinFET dummy-poly opening and planarization process flow article covers the critical transition from SD completion into the RMG replacement sequence [P2].

The interactive flow link lets you navigate step by step, observing how each module's output becomes the next module's entry condition — a principle that is central to understanding why SD integration quality is so consequential at 7nm [T1].

Related Learning Paths

Engineers studying the 7nm FinFET source-drain integration should follow several adjacent learning paths to build a complete picture [P1]. The first is the gate stack integration path, which explains how the dummy gate defined before SD integration is later replaced by the high-k/metal gate stack, and how spacer integrity during SD processing directly affects the RMG trench definition [P1][P2]. The second is the dummy-poly opening and planarization path, which covers the ILD0 deposition and CMP steps that protect the SD structure while preparing for gate replacement [P2].

A third valuable path explores the broader evolution from planar MOSFET to FinFET and beyond to gate-all-around (GAA) structures, which contextualizes why the SD module's design principles — particularly spacer engineering and strain-optimized epitaxy — evolved as they did at 7nm [P1][P2]. The transition to GAA devices, including nanosheet and forksheet architectures, changes the SD integration approach significantly, as inner spacers and suspended channel structures introduce new physical and chemical mechanisms [A1][A2].

Future Outlook

Looking beyond 7nm, the SD integration module faces fundamental transformations [P2]. Gate-all-around (GAA) nanosheet transistors replace the fin geometry with suspended sheet channels, requiring inner spacer formation through lateral etching of sacrificial layers — a process with fundamentally different physics than the conformal-deposition-and-etchback approach used for FinFET spacers [A1][A2]. The source/drain epitaxy in GAA devices must grow on the exposed ends of multiple vertically stacked nanosheets, introducing new selectivity and faceting challenges [A1].

Emerging channel materials such as graphene nanosheets, formed through thermal decomposition of silicon carbide, offer ultra-high carrier mobility but require entirely new SD integration approaches since conventional silicon-based epitaxy and silicidation are not directly applicable [A1]. Stacked forksheet architectures add further complexity by requiring dielectric wall isolation between adjacent devices and independent gate biasing, which changes how spacers, source/drain regions, and contacts are arranged in three dimensions [A2].

The core integration principles remain — self-alignment, strain engineering, series resistance minimization, and parasitic capacitance control — but the physical and chemical mechanisms that implement them will continue to evolve as device architectures advance beyond the 7nm FinFET generation [P1][T3].