28nm Planar FlowPreview

Read the material role and the module order

This teaching Flow places high-k formation in GATE before source/drain processing, and final metal replacement in the later RMG module. Metal-gate-last therefore does not mean high-k-last here. The earlier dielectric still experiences the intervening process history.

For deposition questions, follow what a film does and which module uses or removes it. A module or material name does not prove that every deposition uses LPCVD. The map below connects isolation, gate formation, source/drain processing, replacement and interconnects; detailed Steps retain their access limits. This is one teaching sequence, not a universal implementation for every process bearing the same node label.

Map electrostatic questions to structures

Well-related processing changes semiconductor regions; the gate stack establishes coupling and alignment; source/drain processing forms terminal regions beside the channel. These are different contributions. A nominal threshold shift does not by itself establish reduced drain influence or lower connection resistance. Use the module order to identify which structure each operation changes. This overview contains no transfer curves or extracted DIBL values.

Isolation and wells establish the starting structure

The AA and STI modules define active areas and dielectric isolation. Pattern transfer defines where material is removed, while dielectric filling and planarization establish the resulting isolation structure. Coverage and filling are different tasks: coating a trench does not by itself establish that it has been filled without a void.

Well-related processing establishes regions that contribute to transistor electrostatics and isolation. These regions exist before later gate and source/drain operations, so later thermal exposure becomes part of their process history. Reading the modules in order helps distinguish structure creation from later modification of that structure.