Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
Fundamental Principles of Surface Cleaning in Advanced Semiconductor Manufacturing: Physical Mechanisms, Chemical Kinetics, and Node Evolution
Surface cleaning prepares a specified surface for the next process. The linked cleaning stations give context; contamination and downstream benefit require measurement.
Engineering the Thin Film Resistor: Physical Principles, BEOL Integration, and Advanced Node Evolution
In the design of modern integrated circuits (ICs), passive components are just as critical to overall system performance as active transistors.
Fundamental Principles of Ammonium Peroxide Mixture in Advanced Semiconductor Manufacturing
In microelectronics fabrication, maintaining an ultra-clean wafer surface is a prerequisite for achieving high device yield and reliability.
Fundamentals of Amorphous Carbon Films in Advanced Semiconductor Patterning: Physics, Deposition, and Integration
In modern integrated circuit fabrication, the continuous scaling of feature sizes presents severe challenges to traditional optical lithography and pattern transfer schemes.
Fundamental Principles of Capping Layers in Advanced Semiconductor Manufacturing: Physics, Integration, and Engineering Evolution
In the pursuit of relentless device scaling dictated by Moore's law, modern semiconductor manufacturing has transitioned from simple, homogeneous material systems to highly…
Advanced Contact Metallization: Physical Principles and Integration of Cobalt Silicide (CoSi₂)
As integrated circuit scaling advanced deep into the sub-micron regime, parasitic resistance at the source, drain, and gate electrodes became a dominant bottleneck limiting…
Dilute HF: Oxide Cleaning and Selectivity Limits
DHF can remove selected silicon oxides, but dilution does not guarantee a stop on silicon or neighboring films. Selectivity and the post-clean interface need verification.
Dummy Gate in Replacement Metal Gates
What is a dummy gate in a gate-last transistor? Learn why the temporary gate is patterned, later removed, and replaced, with the current 14nm Flow overview as orientation.
High Aspect Ratio: Etch Deep, Fill Void-Free
High aspect ratio (HAR) processing pairs deep anisotropic etch with void-free gap fill: ion directionality and sidewall passivation set how deep you can cut; Knudsen transport and sticking coefficients set how well you can fill.
Deep Dive into In-Situ Steam Generation (ISSG) in Semiconductor Processing: Physics, Kinetics, and Integration
In modern complementary metal-oxide-semiconductor (CMOS) fabrication, the synthesis of high-quality silicon dioxide ($\text{SiO}_2$) thin films with precise atomic-level control…
Engineering the Interfacial Bridge: Principles, Mechanisms, and Integration of Liner Layers in Advanced Semiconductor Manufacturing
In the intricate architecture of modern integrated circuits, feature dimensions have scaled deep into the nanometer regime.
Fundamental Principles of Nickel Silicide in Advanced Semiconductor Contact Engineering
In modern very large scale integration (VLSI) devices, establishing high-quality electrical contacts between active semiconductor regions and the metal routing network is a…