Fundamental Principles of Ammonium Peroxide Mixture in Advanced Semiconductor Manufacturing

Introduction

In the field of microelectronics fabrication, maintaining an ultra-clean wafer surface is a prerequisite for achieving high device yield and reliability [P3]. Ammonium peroxide mixture (APM), widely known as Standard Clean 1 (SC1) or ammonia peroxide mixture, has served as a cornerstone of wet chemical cleaning for over five decades [A1]. Originally developed as part of the classic RCA clean sequence, this basic chemical mixture remains indispensable in modern semiconductor fabs [A1, T1].

The primary utility of an APM clean lies in its dual capability to remove organic surface contaminants, light metallic residues, and particulate contamination from both silicon and dielectric surfaces [T1, P3]. Its application is vast, spanning critical processing windows in the front end of line (FEOL) for gate dielectric preparation, middle of line (MOL) contact formation, and back end of line (BEOL) post-planarization steps [P1, P3]. Despite the continuous scaling of transistors, the industry continues to rely on the fundamental chemical and physical mechanisms of APM, adapting this highly robust chemistry to meet the stringent demands of advanced technology nodes [A1, A2].

Physics & Mechanism

The operational efficacy of the ammonium peroxide mixture is governed by a dynamic thermodynamic equilibrium between simultaneous surface oxidation and controlled chemical dissolution [P1, T1]. This binary cleaning chemistry consists of ammonium hydroxide ($NH_4OH$), hydrogen peroxide ($H_2O_2$), and deionized water ($DIW$) [P2]. Each component plays a specific role in a coupled chemical reaction chain (Engineering Practice).

Oxidation Kinetics

Hydrogen peroxide acts as a highly potent oxidizing agent [T1]. Upon exposure to the silicon substrate, $H_2O_2$ drives the oxidation of the bare silicon surface to form a thin, self-limiting chemical silicon dioxide ($SiO_2$) layer [T1]. This reaction can be conceptually represented as:

$$\text{Si} + 2\text{H}_2\text{O}_2 \rightarrow \text{SiO}_2 + 2\text{H}_2\text{O}$$

Simultaneously, the high oxidation potential of the peroxide breaks down surface organic impurities, converting them into soluble carbon dioxide and water molecules, which are easily swept away by the fluid flow [T1].

Dissolution and Etching

Concurrently, ammonium hydroxide dissociates in the aqueous solution to produce hydroxide ions ($OH^-$) [P1]. These hydroxide ions act as a chemical etchant that slowly dissolves the chemically grown $SiO_2$ layer [P1]:

$$\text{SiO}_2 + 2\text{OH}^- \rightarrow \text{H}_2\text{SiO}_4^{2-} \text{ (and other soluble silicate complexes)}$$

The coexistence of the oxidizing agent and the etchant establishes a continuous, cyclic process [T1]. The silicon surface is oxidized by $H_2O_2$ and subsequently dissolved by $NH_4OH$ [P1, T1]. This steady, isotropic etching slowly peels away the outermost atomic layers of the wafer substrate, ensuring that any contaminants bound to or embedded within the native oxide are physically detached [P3].

Particle Lift-Off and Zeta Potential

The physical removal of sub-micron particles during an APM clean is primarily achieved through this controlled under-cutting mechanism [P3]. As the $OH^-$ ions diffuse underneath a adhering particle and etch the supporting oxide matrix, the physical anchor of the contaminant is destroyed [P3].

Once the particle is liberated from the surface, electrostatic forces prevent its redeposition [P3]. In the highly alkaline pH environment established by the ammonium hydroxide, both the silicon dioxide wafer surface and the majority of suspended particulate contaminants (such as silica or ceria slurry particles) acquire a negative surface charge [P3]. This surface charge behavior is described by the electrostatic double-layer theory, where the electrostatic potential at the boundary of the diffuse layer is defined as the zeta potential [P3]. Because both the wafer substrate and the particles exhibit negative zeta potentials, a strong electrostatic repulsion barrier is created [P3]. This repulsive force overcomes attractive Van der Waals forces, ensuring that particles remain suspended in the bulk liquid and are successfully flushed from the chamber [P3].

Process Principles

Optimizing the performance of an APM clean requires a deep understanding of how various process parameters directionally influence cleaning efficiency, material loss, and surface morphology [P3].

• Chemical Concentration Ratio ($NH_4OH : H_2O_2 : H_2O$): The relative volumetric ratio of the components dictates the balance between oxidation and etching [T1]. Increasing the concentration of ammonium hydroxide relative to hydrogen peroxide shifts the equilibrium toward a faster $SiO_2$ etch rate [P1]. However, if the hydrogen peroxide concentration drops too low, the protective chemical oxidation of the silicon surface cannot keep pace with the dissolution rate [T1]. Under these conditions, the free hydroxide ions aggressively attack the bare silicon lattice, causing severe crystallographic etching and surface roughening [P1, T1].
• Temperature: Elevating the temperature of the chemical bath increases the reaction rate constants exponentially, adhering to Arrhenius kinetics (Engineering Practice). While this significantly enhances both organic decomposition and particle lift-off efficiency, it also accelerates the thermal decomposition of hydrogen peroxide into water and oxygen gas [T1]. Consequently, excessively high temperatures destabilize the chemical mixture, altering the concentration ratio over time and reducing process reproducibility [T1].
• Process Time: The duration of the clean must be carefully balanced (Engineering Practice). While longer exposure times ensure the complete removal of stubborn particles and organics, they also lead to cumulative material loss of both silicon and dielectric layers [P2]. In advanced manufacturing, process times are minimized to preserve delicate, ultra-thin physical features [P1, P2].
• Mechanical Agitation (Megasonic Energy): To assist chemical lift-off, high-frequency megasonic acoustic waves are frequently introduced into the cleaning chamber (Engineering Practice). Megasonic energy generates acoustic streaming and localized micro-cavitation within the fluid boundary layer, providing the physical momentum necessary to overcome the adhesion forces of sub-micron particles without causing physical damage to fragile wafer features (Engineering Practice).
• Fluid Film Preservation: During the transition between chemical cleaning, rinsing, and drying phases, maintaining a continuous liquid film on the wafer surface is critical [A2]. If the liquid film ruptures, surface tension gradients (Marangoni effect) pull dissolved impurities toward the dry-wet boundary, resulting in localized drying defects and watermark formation [A2].

Challenges & Failure Modes

While APM is an exceptionally effective cleaning agent, its chemical reactivity introduces several critical failure modes that must be carefully managed, particularly in high-precision device fabrication [P3].

Degradation of Gate Oxide Integrity

In dual-gate-oxide integration schemes, thick gate oxides undergo repeated lithography, etching, and cleaning cycles [P1]. If APM is utilized inappropriately as a post-etch clean, the alkaline nature of the chemistry can severely degrade the dielectric performance [P1]. The $OH^-$ ions in the APM solution cause microscopic, non-uniform etching of the silicon dioxide surface [P1]. This increases surface micro-roughness, creating localized physical peaks and valleys [P1]. Under operational bias, these physical surface micro-roughness points act as local electric field enhancement sites, which accelerate charge trapping, lower the dielectric breakdown voltage, and degrade gate oxide integrity [P1]. For these reasons, highly stable, non-etching acidic clean steps like sulfuric peroxide mixture (SPM) are preferred for critical gate-dielectric interfaces where surface planarity is paramount [P1].

Dopant Loss in Ultra-Shallow Junctions

For sub-100 nm CMOS technologies, source/drain extension (SDE) regions are formed using ultra-low-energy ion implantation to produce ultrashallow junctions (USJ) [P2]. In these structures, the dopant profile (such as arsenic for n-type junctions) is positioned extremely close to the surface, with peak concentrations residing within the top few nanometers of the silicon lattice [P2].

Because an APM clean systematically consumes and etches a thin layer of silicon during its oxidation-dissolution cycle, repeated exposures to the cleaning chemical can "shave off" the highly doped surface peak [P2]. This dopant loss dramatically reduces the active carrier concentration and activated dopant dose within the junction [P2]. According to semiconductor device physics, a reduction in carrier concentration shifts the Fermi level and increases the sheet resistance of the SDE region [P2, T2, T3]. This parasitic resistance directly degrades the transistor's drive current and overall switching speed [P2]. Interestingly, p-type dopants (such as boron) are less susceptible to this failure mode due to differences in their physical depth profiles and chemical segregation behavior [P2].

Metallic Cross-Contamination

In the high-pH regime of APM, certain transition metal ions (such as iron or copper) can form insoluble hydroxide precipitates on the wafer surface [T1]. Although the high oxidation potential of hydrogen peroxide generally complexes and solubilizes many Group IB and IIB metals, the lack of a strong acid means that trace metals can easily redeposit onto the active silicon area [T1]. This necessitates a subsequent low-pH cleaning step, such as hydrochloric acid-peroxide mixture (HPM or SC2), to dissolve these metallic precipitates via chlorine-metal complexation [T1, P3].

Technology Node Evolution

The application of the ammonium peroxide mixture has evolved significantly as the industry transitioned from planar transistors to complex three-dimensional architectures [P3].

Technology Node	Device Architecture	APM Implementation Strategy	Key Technical Challenges
28nm	Planar CMOS 28nm Planar Flow	High-concentration batch immersion cleaning [T1]	Gate oxide scaling, basic organic residue removal [P1, T1]
14nm	3D FinFET 14nm FinFET	Highly diluted APM mixtures, single-wafer processing [T1, A2]	Fin erosion, preservation of high-k gate stack integrity [P1, T1]
7nm and beyond	GAA Nanosheet / CFET 7nm FinFET	Ultra-dilute APM with physical megasonic control and IPA drying [A2]	Capillary-force pattern collapse, extreme dopant loss in USJ [P2, A2]

During the 28nm node era, planar transistors featured relatively large, robust structural geometries (Engineering Practice). Batch cleaning systems utilizing highly concentrated APM solutions at elevated temperatures were standard, as the devices could tolerate moderate silicon loss and minor surface roughening [T1].

With the introduction of the 14nm FinFET node, the physical dimensions of the silicon channels became extremely thin, and high-k metal gate (HKMG) stacks were introduced [P1]. The aggressive etching behavior of traditional APM would easily erode the delicate vertical silicon fins and damage the sensitive metal gate materials [P1]. To overcome this, the industry shifted toward ultra-dilute APM chemistries, operating at lower temperatures to minimize the etch rate while still leveraging the electrostatic particle repulsion driven by the negative zeta potential [P3, T1].

At the 7nm FinFET node and beyond, structural aspect ratios increased dramatically [T1]. In these dense, high-aspect-ratio architectures, the surface tension of water-based cleaning fluids can induce massive capillary forces during the drying phase, leading to physical pattern collapse [P3]. This forced the transition from batch immersion systems to highly automated single-wafer cleaning tools [A2]. These modern single-wafer systems dynamically control chemical delivery, maintaining a continuous, thin liquid film on the wafer surface to prevent drying hot spots, and utilize advanced isopropyl alcohol (IPA) drying techniques to eliminate capillary-induced structural damage [A2]. Furthermore, the strict physical material budgets at the sub-7nm scale mean that any APM clean must operate under an atomic-scale etching budget, allowing only sub-nanometer oxide dissolution per run [P2].

Related Processes

To build a highly reliable integrated circuit, the APM clean must be integrated harmoniously with adjacent processing steps [P3].

• Sulfuric Peroxide Mixture (SPM) Cleaning: Typically, an SPM step is performed prior to the APM step [P1]. SPM relies on an extremely aggressive sulfuric acid and hydrogen peroxide reaction to decompose thick bulk photoresist layers and heavy organic contaminants, leaving the subsequent APM step to focus on fine particulate removal and light organic polishing without attacking the silicon substrate [P1, P3].
• Hydrofluoric Acid (HF) Etching: An oxide strip using diluted hydrofluoric acid (DHF) is often positioned before or after the APM step [A2]. Applying DHF after APM removes the chemical oxide grown by the hydrogen peroxide, leaving a clean, hydrophobic, hydrogen-terminated silicon surface ready for subsequent epitaxial growth or thin-film deposition [P1].
• Chemical Mechanical Planarization (CMP): Following CMP steps (for oxide, tungsten, or copper), the wafer is heavily contaminated with slurry abrasives and organic additives [P3]. Post-CMP cleaning processes heavily utilize modified APM solutions combined with physical scrubbing using polyvinyl alcohol (PVA) brushes to lift off and repel adhering slurry particles [P3].
• Alternative Alkaline Chemistries: Developers like tetramethylammonium hydroxide (TMAH) are used in lithography and selective etching [A2]. Unlike the isotropic and polishing action of APM, TMAH exhibits highly anisotropic etching characteristics on silicon, making APM the preferred choice when uniform, non-directional surface cleaning is required [A2].
• Laser-Assisted Wet Cleans: Modern research is exploring the integration of physical laser energy with chemical cleaning [A1]. In these composite systems, a pulsed laser is used to induce photothermal desorption of stubborn contaminants, allowing the APM chemistry to dissolve and carry away the loosened particles with significantly reduced chemical consumption [A1].

Future Outlook

As the semiconductor industry marches toward Gate-All-Around (GAA) nanosheets and stacked Complementary FET (CFET) architectures, the physical limits of wet cleaning are being pushed to their absolute boundaries [P3].

The primary research vector for future clean technologies involves the development of ultra-low surface tension cleaning formulations (Engineering Practice). Because horizontal nanosheet channels present narrow physical cavities where liquid exchange is highly restricted, standard water-based APM solutions struggle to penetrate and refresh within the channels (Engineering Practice). Researchers are formulating novel non-aqueous and solvent-based cleaning mixtures that possess exceptionally low viscosity and surface tension, allowing the active chemical agents to diffuse freely into nanometer-scale horizontal trenches without causing structural damage (Engineering Practice).

Additionally, environmental and sustainability mandates are driving the development of "green" clean initiatives [T1]. The thermal decomposition of hydrogen peroxide and the evaporation of ammonia gas generate substantial chemical vapors that require complex exhaust scrubbers and wastewater treatment systems [T1]. Emerging systems are exploring the use of ultrapure water pre-dissolved with reactive gases, such as ozone ($O_3$) or hydrogen ($H_2$), to completely replace traditional APM and HPM chemical baths [T1]. These gas-dissolved water systems provide similar oxidation and particle-removal characteristics but naturally revert to harmless water and oxygen upon disposal, drastically reducing the environmental footprint of high-volume semiconductor manufacturing [T1].

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References

• [P1] J. S. Yang et al., "Thick Gate Oxide Integrity Improvement by Sulfuric Peroxide Mixture Cleaning after Thick Gate Oxide Etch," Journal of The Electrochemical Society, vol [P1]. 153, no. 9, pp. G866-G869, 2006.
• [P2] H. S. Cha et al., "Dopant loss of ultrashallow junction by wet chemical cleaning," IEEE Transactions on Electron Devices, 2006 [P2].
• [P3] H. J. Kim, "Chemical Mechanical Planarization-Related to Contaminants: Their Sources and Characteristics," in Emerging Contaminants, IntechOpen, 2020 [P3].
• [T1] J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling, Prentice Hall, 2000 [T1].
• [T2] C. Hu, Modern Semiconductor Devices for Integrated Circuits, Prentice Hall, 2010 [T2].
• [T3] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed [T2]., Wiley-Interscience, 2006 (Engineering Practice).
• [A1] "Composite cleaning process and system," US Patent US-2025326009-A1, 2024.
• [A2] "Substrate processing system and substrate processing method," US Patent US-2025210391-A1, 2023.