High Aspect Ratio: Etch Deep, Fill Void-Free

High aspect ratio (HAR) processing is the etch-plus-deposition toolkit for building structures whose depth or height greatly exceeds their width: the etch leg cuts deep, straight trenches — balancing ion directionality against sidewall passivation — and the deposition leg fills those narrow gaps void-free — balancing vapor transport against low sticking coefficients. From deep trench isolation (DTI) in analog devices and DRAM capacitor trenches to the vertical channels of 3D NAND [P3], the more devices grow into the third dimension, the more these two pillars gate yield and performance. One sentence grades a HAR process: etch deep, and fill without voids.

The Four Stages of a Deep Trench's Life

In the 40nm image sensor's deep trench isolation, a trench's production life compresses into four stages — open, etch, fill, planarize — the two HAR pillars handing off to each other.

1. Hard-mask opening: an anisotropic oxide hard-mask etch defines where the trench will go.
2. Deep silicon etch: reactive ion etching drives the trench vertically into the substrate — several times deeper than wide, sidewalls standing straight.
3. Gap fill: liner and bulk dielectric deposition fill the narrow trench without voids.
4. Planarization: CMP grinds off the excess and reveals an isolation structure flush with the substrate.

Physics & Mechanism

Knudsen Diffusion: The Transport Tax at Depth

Inside a HAR trench, the gas mean free path often exceeds the feature width — molecules hit the sidewalls far more often than each other, and transport is governed by Knudsen diffusion. Reactant delivery to the bottom is limited by molecular conductance, with precursor concentration falling exponentially with depth. For uniform deposition or etching along the full depth, surface reaction rates must sit well below transport rates — the surface-reaction-limited regime is the only safe zone.

Sticking Coefficients: Stick or Bounce

Deposition conformality is set by the precursor sticking coefficient β — the probability that a molecule reacts into film upon surface impact rather than desorbing. A β near 1 reacts on first collision at the trench mouth, snapping the opening shut (pinch-off) and sealing in a large void; a low-β precursor (TEOS versus silane, for instance) bounces between sidewalls and migrates to the very bottom before reacting — the origin of conformal gap fill [T1].

Ion Directionality: IADF and Passivation

Anisotropic deep etching relies on the plasma sheath's electric field accelerating ions vertically; the narrower the ion angular distribution function (IADF), the more vertical the attack. Sheath collisions broaden the IADF, and oblique ions strike the upper sidewalls, lose energy, and undercut. Deep silicon etching therefore cycles etch with polymer passivation (the Bosch process) — ion bombardment clears the bottom while polymer protects the walls; advanced nanostructures switch to self-limiting oxygen-plasma passivation to avoid polymer residue.

Process Principles

The Deposition Side

• Reactor pressure: sub-atmospheric operation (SACVD) balances mean free path against gas density; over-pressurizing adds gas-phase collisions and slides the process into the mass-transport-limited regime, degrading conformality.
• Ozone-to-TEOS ratio: more O₃ drives precursor decomposition, cuts carbon impurities, and improves density and step coverage — at the directional cost of total deposition rate.
• Substrate temperature: heat gives adsorbed precursors surface-mobility energy to migrate deeper; past a threshold, reactions accelerate into the mass-transport-limited regime and the trench mouth seals early into a void.

The Etch Side

• RF bias power: raising sheath potential and ion energy sharpens the IADF, accelerates sputter-clearing of bottom passivation, and speeds vertical etch — until mask selectivity and substrate damage give way.
• ICP pressure: lowering pressure in an inductively coupled plasma reactor reduces sheath collisions, narrows the IADF, and straightens profiles; too low, and neutral radical density starves the total etch rate.
• Passivation-to-etch ratio: in SF₆/O₂ chemistry, fluorine etches while oxygen passivates; more O₂ thickens the protective SiOxFy sidewall layer and suppresses undercut — until the bottom passivation grows thicker than ions can clear (etch stop).

Challenges & Failure Modes

• Voids and pinch-off: precursor flux peaks at the trench top (line-of-sight and shading), so top corners always deposit thicker than lower walls; non-conformal coverage lets the corners merge before the bottom fills — buried voids later surface during planarization or etch as chemical residue, shorts, or collapse.
• Aspect-ratio-dependent etching (ARDE, RIE lag): narrow trenches exhaust by-products (SiF₄) and starve etchant radicals (F) faster than wide ones, so their bottoms etch slower — wide trenches over-etch while narrow ones undershoot on the same wafer.
• Microtrenching and profile distortion: ions reflected off tilted sidewalls focus onto bottom edges, cutting fine trenches through thin stop layers; mask retreat unmasks the incoming flux and transfers a taper onto the silicon walls.
• Charging effects: light electrons collect near the mask top and upper sidewalls while heavy ions dive to the bottom — the charge separation builds internal fields that deflect incoming ions into asymmetric profiles, mid-wall bows, or outright etch stop.

From Principle to Production Flow

The four stages appear in production as adjacent, named steps. The deep trench isolation module of the 40nm BSI CMOS Image Sensor flow: an oxide hard-mask etch opens the window, an anisotropic silicon trench etch drives the trench vertically into the substrate, and nitride fill plus CMP close the module. From the 40nm flow overview you can walk the whole chain with real cross-sections — a free course flow, so step names, section states, and explanations are publicly visible.

Technology Node Evolution

At the 28nm planar node, HAR challenges concentrated on STI fill and contact etch: TEOS/ozone SACVD and HARP oxides filled moderate aspect ratios void-free, while fluorocarbon plasmas balanced mask selectivity against verticality. The 14nm FinFET node pushed fin-isolation trenches past SACVD's physical limits, calling in FCVD alongside HARP, and demanded highly anisotropic dummy-gate etch and work-function-metal patterning inside high-aspect-ratio cavities. At 7nm and below, line-of-sight and diffusion-limited CVD can no longer guarantee void-free fill — atomic layer deposition with its self-limiting gas-surface reactions becomes mandatory, and etching moves to ALE and cryogenic variants.

Related Processes

HAR is bracketed by its neighbors: before any HAR deposition, a thorough wet clean strips native oxide and residue, and hydrofluoric acid steps need careful drying (isopropyl alcohol) so surface tension doesn't pull adjacent structures into pattern collapse; after fill, a high-temperature anneal densifies porous oxides and erases seams; and CMP closes the loop — charged abrasive slurries control removal rates material by material to suppress dishing and erosion across pattern densities. TEOS and undoped silicate glass anchor the oxide fill's material side, and the chemical vapor deposition family is the technology tree's trunk.

Future Outlook

3D DRAM, CFETs, and 3D NAND beyond a few hundred layers push HAR further: cryogenic etching nearly freezes sidewall chemistry while ion-assisted bottom reactions continue — high anisotropy with minimal passivation; the climate cost of CF₄/C₄F₈/SF₆ drives research into short-lived fluorocarbon alternatives and fluorine-free sequences; and BEOL HAR vias migrate from copper toward cobalt and ruthenium — selective CVD or ALD deposits them directly, bypassing seed and barrier limits for void-free sub-10nm contacts.