Introduction
In the continuous pursuit of Moore's law, semiconductor manufacturing has transitioned from planar structures to complex three-dimensional (3D) architectures . As lateral dimensions scale down, the physical and electrical constraints of materials demand that structures grow vertically to maintain functional performance, surface area, and capacitance [P3, T1]. This scaling paradigm relies heavily on the high aspect ratio (HAR) process—a suite of advanced etching and deposition techniques designed to fabricate features where the depth or height of a structure is significantly larger than its lateral width .
High aspect ratio processes are critical for fabricating essential components across various devices, including Deep Trench Isolation (DTI) in analog devices, capacitor trenches in dynamic random-access memory (DRAM), high-density vertical channels in 3D NAND flash, and advanced isolation in logic devices [P2, P3]. Two primary engineering pillars define these processes: high aspect ratio etching, which selectively removes material to form deep, vertical features, and high aspect ratio deposition, which fills these ultra-narrow gaps without defects [P1, P2].
Historically, conventional chemical vapor deposition (CVD) and isotropic wet etching were sufficient for planar layouts . However, as aspect ratios escalated, issues like shadowing, mass transport limitations, and physical voiding emerged . To overcome these issues, advanced technologies like sub-atmospheric chemical vapor deposition (SACVD), specialized high aspect ratio process (HARP) oxide deposition, and deep reactive ion etching (DRIE) were developed [P1, T1, A1]. Understanding the physical, chemical, and transport mechanisms that govern these processes is essential for modern semiconductor integration .
Physics & Mechanism
The physics of high aspect ratio processes is governed by gas-phase transport dynamics, surface reaction kinetics, and plasma-ion interactions [P2, P3, T1]. When a feature's width scales down to the sub-micron regime, the physical behavior of reactant gases and plasma ions within the trench changes fundamentally compared to open surfaces [T1, P3].
Gas Transport and Knudsen Diffusion
In a standard deposition or etching reactor, reactant gases move via convective flow and molecular diffusion (Engineering Practice). However, inside a high aspect ratio trench, the mean free path of the gas molecules often exceeds the lateral dimensions of the feature . This regime is characterized by a high Knudsen number, where gas transport is dominated by Knudsen diffusion rather than bulk molecular diffusion .
Under Knudsen diffusion, molecules collide far more frequently with the trench sidewalls than with other gas molecules . Consequently, the transport of reactants to the bottom of the trench is limited by molecular conductance, creating a severe concentration gradient where precursor concentration decreases exponentially with depth [P2, T1]. To ensure that deposition or etching occurs uniformly along the entire depth of the trench, the rate of surface reaction must be significantly slower than the rate of transport—a regime known as the surface-reaction-limited regime [T1, T2].
Sticking Coefficients in Deposition
The conformality of a high aspect ratio deposition process is heavily influenced by the sticking coefficient of the precursor molecules . The sticking coefficient ($\beta$) is the probability that a precursor molecule adsorbing onto a surface will react and deposit a solid film rather than desorbing back into the gas phase (Engineering Practice).
High Sticking Coeff *(Engineering Practice)*. (\beta ~ 1) Low Sticking Coeff *(Engineering Practice)*. (\beta << 1)
[Precursor Flux] [Precursor Flux]
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Pinch-off & Voiding Conformal Gap Fill
If a precursor has a high sticking coefficient, it reacts immediately upon its first collision near the top of the trench, leading to rapid deposition at the trench opening and eventual pinch-off, leaving a large void . Conversely, precursors with low sticking coefficients (such as tetraethyl orthosilicate (TEOS) compared to silane) can bounce off the sidewalls multiple times, diffusing deep to the bottom of the feature before reacting . This enables highly conformal undoped silicate glass (USG) or doped oxide deposition [T1, A1].
Plasma Physics and Ion Transport in Etching
Anisotropic high aspect ratio etching relies on plasma-driven reactive ion etching (RIE) to achieve vertical profiles [P2, P3]. The plasma generates chemically reactive radicals and positively charged ions (Engineering Practice). An electric field in the plasma sheath accelerates these positive ions vertically toward the wafer surface [P2, P3].
The directionality of these ions is described by the ion angular distribution function (IADF) . In an ideal anisotropic etch, the IADF is extremely narrow, meaning ions travel perpendicular to the substrate . However, collisions within the plasma sheath can cause ion scattering, broadening the IADF . Ions entering the trench at an angle collide with the upper sidewalls, losing energy and causing unwanted lateral etching, or "undercutting" [P2, P3].
To achieve high anisotropy, the process must maintain a dynamic balance between physical ion bombardment (which removes passivation at the trench bottom) and chemical passivation (which protects the sidewalls from neutral radicals) [P2, P3]. In traditional DRIE, this is accomplished via the Bosch process, which cycles between etching and polymer deposition . In advanced nanostructures, alternative techniques like the Clear-Oxidize-Remove-Etch (CORE) sequence use self-limiting oxygen plasma passivation to avoid polymer residues while maintaining profile control .
Process Principles
Optimizing high aspect ratio processes requires adjusting hardware and chemistry parameters to control reaction rates, ion energies, and transport dynamics [P2, P3, T1].
Deposition Parameter Dependencies
In high aspect ratio chemical vapor deposition, such as sub-atmospheric chemical vapor deposition (SACVD) and high aspect ratio process (HARP) applications, the primary goal is to maximize trench fill capability [T1, A1].
- Chamber Pressure: Operating at sub-atmospheric pressures (SACVD) balances the reactant mean free path and gas density . Increasing pressure raises the concentration of reactive species, which boosts the deposition rate . However, if the pressure is too high, gas-phase collisions increase, which narrows the mean free path and degrades conformality by shifting the process toward the mass-transport-limited regime .
- Reactant Ratio: For silicon dioxide deposition, the ratio of ozone ($O_3$) to TEOS is critical . Increasing the ozone-to-TEOS ratio enhances the decomposition of the organometallic precursor, reducing carbon impurities and improving the film's density and step coverage, though it may directionally decrease the overall deposition rate .
- Substrate Temperature: Raising the temperature increases the thermal energy available for surface diffusion, allowing adsorbed precursors to migrate deeper into the trenches . However, if the temperature is increased beyond a critical threshold, the reaction rate accelerates into the mass-transport-limited regime, causing premature reaction at the trench mouth and causing void formation .
Etching Parameter Dependencies
In plasma etching, process parameters must be tuned to control ion energy, neutral flux, and sidewall passivation [P2, P3].
- RF Bias Power: The radio frequency (RF) bias power applied to the electrostatic chuck determines the sheath potential and the energy of the accelerating ions . Increasing bias power increases ion energy, which sharpens the IADF and increases the vertical etch rate by accelerating the sputter-removal of bottom passivation [P2, P3]. However, excessive bias power can degrade mask selectivity and cause physical damage to the substrate .
- Chamber Pressure: Lowering the chamber pressure in an inductively coupled plasma reactor reduces ion-neutral collisions within the sheath [P2, P3]. This narrows the IADF, improving profile verticality . Conversely, if pressure is too low, the concentration of reactive neutral radicals decreases, which can reduce the overall chemical etch rate .
- Passivation-to-Etchant Gas Ratio: In chemistries such as $SF_6/O_2$, fluorine atoms act as the primary etchant while oxygen acts as the passivating agent [P2, P3]. Increasing the $O_2$ flow rate relative to $SF_6$ increases the thickness of the protective silicon oxyfluoride ($SiO_xF_y$) passivation layer on the sidewalls, which reduces lateral undercutting [P2, P3]. However, an excessively high passivation ratio can lead to "etch stop," where the bottom passivation layer becomes too thick for the ions to clear .
Challenges & Failure Modes
As aspect ratios exceed critical thresholds, physical, chemical, and mechanical failure modes can compromise device yield and performance [P1, P2, P3].
Void Formation and Pinch-off
Void formation is the primary failure mode in high aspect ratio trench filling [T1, A1]. Because the flux of arriving precursor molecules is highest at the top of the trench (due to line-of-sight and shadow effects), deposition is always thicker at the top corners than on the lower sidewalls .
If the step coverage is non-conformal, these top corners will merge, or "pinch off," before the bottom of the trench is completely filled . This traps an unfilled cavity, or void, inside the structure [T1, A1]. During subsequent planarization or etching steps, these buried voids can be exposed, leading to chemical entrapment, electrical shorts, or mechanical collapse [A1, A2].
Step 1: Asymmetric Deposition Step 2: Pinch-Off (Void)
[Precursor Flux] [Precursor Flux]
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Aspect Ratio Dependent Etching (ARDE)
Also known as RIE lag, Aspect Ratio Dependent Etching (ARDE) is a transport-limited phenomenon where smaller, narrower trenches etch slower than wider trenches on the same die . As a trench deepens, the transport of volatile reaction products (such as $SiF_4$) out of the trench and the diffusion of fresh etchant radicals (such as $F$ atoms) to the bottom become severely restricted .
This local depletion of reactants and accumulation of products reduces the net etch rate at the bottom of high aspect ratio features . Consequently, across a wafer with varying feature sizes, wider trenches will over-etch into the underlying layers before narrower trenches reach their target depth .
Microtrenching and Profile Distortion
Microtrenching occurs when ions bounce off the sloped sidewalls of a trench and focus at the outer edges of the trench floor . This localized increase in ion flux creates deep, trench-like gouges at the bottom corners of the feature, which can punch through thin underlying stop layers (Engineering Practice).
Additionally, mask retraction and erosion during prolonged etching can degrade profile control . As the mask edge erodes laterally, the incoming ion flux is no longer shielded, transferring a positive or negative taper to the silicon sidewalls and distorting the target geometry .
Charging Effects and Ion Twisting
During plasma etching, the high-aspect-ratio feature acts as an electrostatic capacitor . Because electrons are light and have highly isotropic angular distributions, they preferentially collect near the top of the insulating mask and the upper trench sidewalls . In contrast, heavy positive ions possess high vertical momentum and penetrate deep to the bottom of the trench .
This spatial separation of charge creates a strong localized electric field within the feature . This internal field can deflect incoming positive ions away from the vertical path, leading to asymmetric profile twisting, bowing of the middle sidewalls, or complete etch stop [P2, P3].
Technology Node Evolution
The integration of high aspect ratio processes has evolved significantly across technology nodes, reflecting the transition from planar devices to 3D nanostructures [28nm Planar Flow](/flow/cmm5rxyr300009qfq2qwnesdj, 14nm FinFET](/flow/cmm5rweze00005ifqn28dmhbz) .
| Technology Node | Primary HAR Application | Dominant Deposition Tech | Dominant Etching Tech | Key Physical Limitation |
|---|---|---|---|---|
| 28nm 28nm Planar Flow | Shallow Trench Isolation (STI) | SACVD / HARP | Conventional RIE (Engineering Practice) | Aspect Ratio Dependent Etching (ARDE) |
| 14nm 14nm FinFET | Fin Isolation & Replacement Gate | HDP-CVD / FCVD / SACVD [A1, A2] | Inductively Coupled Plasma (ICP) RIE | Sidewall Passivation Control & Gate Pinch-off |
| 7nm & Beyond 7nm FinFET | High-k Metal Gate & Deep Vias | Atomic Layer Deposition (ALD) (Engineering Practice) | Atomic Layer Etching (ALE) / Cryogenic Etch (Engineering Practice) | Radical Transport & Atomic-scale Damage (Engineering Practice) |
28nm Planar Node
At the 28nm planar node 28nm Planar Flow, high aspect ratio challenges were primarily focused on Shallow Trench Isolation (STI) filling and contact hole etching . Gap fill was successfully managed using sub-atmospheric chemical vapor deposition (SACVD) and high aspect ratio process (HARP) oxide technologies, utilizing TEOS and ozone chemistry to fill moderately high-aspect ratio trenches without voids [T1, A1]. Etching relied on steady-state fluorocarbon plasma processes to maintain a balance between mask selectivity and vertical profile control .
14nm FinFET Node
With the introduction of the 14nm FinFET node 14nm FinFET, the transition to 3D active channels significantly increased the aspect ratio of the isolation trenches between silicon fins [A1, A2]. Traditional SACVD was pushed to its physical limits, prompting the integration of Flowable Chemical Vapor Deposition (FCVD) alongside HARP to fill the high aspect ratio gaps between closely spaced fins [A1, A2]. On the etching side, replacement metal gate (RMG) processing required highly anisotropic dummy gate etching and precise work-function metal patterning within narrow, high aspect ratio cavities [A1, A2, T2].
7nm Node and Beyond
At the 7nm node 7nm FinFET and beyond, the aspect ratios of contacts, vias, and metal gate trenches became so extreme that conventional line-of-sight and diffusion-limited CVD technologies could no longer guarantee void-free fill . Atomic Layer Deposition (ALD)—which relies on sequential, self-limiting gas-surface reactions—became mandatory to achieve true atomic-scale conformality (Engineering Practice). Similarly, etching evolved toward Atomic Layer Etching (ALE) and low-temperature cryogenic etching, minimizing physical damage while maintaining perfect anisotropy at the atomic level [P2, (Engineering Practice)].
Related Processes
High aspect ratio processes do not exist in isolation; they are highly integrated with adjacent manufacturing steps to ensure overall device structural integrity and electrical performance [P1, A1].
[ Surface Clean ]
│ (Removes native oxide and particulates)
▼
[ High-Aspect Ratio Fill ] ──► [ Post-Deposition Anneal ] ──► [ Chemical Mechanical Planarization ]
(SACVD / HARP / FCVD) (Densification & Reflow) (Planarization of Overburden)
Chemical Mechanical Planarization (CMP)
Following the deposition of a thick high aspect ratio oxide or metal fill, the wafer has a highly non-uniform overburden [A1, A2]. Chemical Mechanical Planarization (CMP) is used to polish back this excess material and planarize the surface [A1, A2].
In advanced replacement gate integration, CMP slurries containing charged abrasive nanoparticles are utilized to control the relative removal rates between different materials, such as dummy structures and active gates [A1, A2]. This helps minimize dishing and erosion caused by pattern density variations [A1, A2].
Post-Deposition Annealing
Oxides deposited at sub-atmospheric or lower temperatures (such as SACVD or PECVD films) are often porous and non-stoichiometric . To improve their dielectric strength and etch resistance, these films undergo high-temperature annealing . This thermal treatment densifies the oxide film, removes volatile organic precursors and moisture, and can induce structural reflow to eliminate microscopic boundary interfaces or seam defects .
Wet Clean and Surface Preparation
Prior to any high aspect ratio deposition, the trench or contact hole must undergo an aggressive wet clean process . This step removes native oxide, organic residues, and metallic contaminants without damaging the fragile, high aspect ratio structures [T2, (Engineering Practice)].
Using chemistries like dilute hydrofluoric acid requires careful drying control (such as isopropyl alcohol drying) to prevent surface tension from pulling adjacent high aspect ratio structures together, which can cause pattern collapse .
Future Outlook
As the semiconductor industry advances toward 3D DRAM, complementary field-effect transistors (CFETs), and high-layer-count 3D NAND (exceeding several hundred layers), high aspect ratio processes will continue to be a primary area of technological innovation .
One major trend is the development of ultra-low temperature cryogenic etching . By lowering the wafer temperature during plasma etching, the chemical reaction rate on the sidewalls is reduced to near zero, while ion-assisted reactions at the bottom continue . This approach enables highly anisotropic profiles with minimal sidewall passivation, reducing polymer residue and profile distortion .
Additionally, the environmental impact of conventional greenhouse gases used in HAR etching (such as $CF_4$, $C_4F_8$, and $SF_6$) is driving research into alternative, shorter-lifetime fluorocarbon chemistries or entirely fluorine-free etching sequences [P3, (Engineering Practice)].
Finally, in the back-end-of-line (BEOL) interconnects, high aspect ratio vias are transitioning from copper to alternative metals like cobalt or ruthenium . These metals can be deposited using selective chemical vapor deposition or ALD, which bypasses the traditional seed-layer barrier limits and enables void-free fill of sub-10nm contact holes .