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SemiFlows
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Technical Blog

Deep dive into the physics and integration logic of semiconductor manufacturing

DepositionSep 11, 20265 min read

Film Uniformity vs Step Coverage: Two Spatial Questions

Understand why wafer-scale film uniformity, local step coverage and complete gap filling are separate observations.

Device PhysicsSep 11, 20265 min read

Gate Work Function vs Channel Doping in Threshold Control

Understand how gate work function and channel doping affect different parts of MOS threshold electrostatics.

Device PhysicsSep 11, 20265 min read

High-k Gate Dielectrics: Capacitance Is Not Leakage

Separate gate capacitance, equivalent oxide thickness and leakage when comparing high-k dielectric stacks.

Ion ImplantationSep 11, 20265 min read

Implant Dose vs Active Dopants: Count the Right Thing

Understand why delivered implant dose, chemical concentration, active dopants and mobile carriers are different quantities.

Device PhysicsSep 11, 20265 min read

Interface Traps vs Fixed Charge: Different MOS Responses

Separate persistent charge contributions from dynamic interface-trap response in MOS devices.

Device PhysicsSep 11, 20265 min read

Isolation vs Junction Leakage: Trace the Unwanted Current

Trace unwanted current paths to distinguish isolation-related and junction leakage without assuming they are exclusive.

Ion ImplantationSep 11, 20265 min read

LDD vs Halo Implants: Two Different Electrostatic Jobs

Compare LDD and halo doping through their locations, polarities, electrostatic roles and resistance tradeoffs.

LithographySep 11, 20265 min read

Overlay vs Pattern Edge Error: Which Boundary Moved?

Separate pattern translation, width change and local edge variation to understand overlay and edge-placement error.

InterconnectSep 11, 20265 min read

Single vs Dual Damascene: Follow the Fill Sequence

Compare single and dual damascene by tracking when vias and lines are filled, planarized and connected.

Device PhysicsSep 11, 20265 min read

STI vs DTI in Image Sensors: Trace the Isolation Path

Compare STI and DTI by tracing the electrical and optical paths that an image-sensor boundary must control.

InterconnectSep 11, 20265 min read

Via-First vs Trench-First: Track the Exposed Surfaces

Follow exposed surfaces and temporary materials to understand via-first and trench-first dual damascene.

Process IntegrationSep 11, 20265 min read

Why Replacement Metal Gate Starts with a Dummy Gate

Understand how a dummy gate preserves geometry and what must remain intact when the final metal gate replaces it.

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SemiFlows

Semiconductor process knowledge — flow visualization + Flow-aware, evidence-linked Q&A

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© 2026 SemiFlows. All rights reserved.

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