Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
Microloading and ARDE: Separate Neighborhood and Access
Compare neighborhood loading and feature access to understand microloading and aspect-ratio-dependent etching.
Etch Selectivity vs Anisotropy: Material or Direction?
Distinguish material selectivity from directional etching, and see why neither property alone proves pattern quality.
Contact Etch Stop Layer (CESL): Principles, Stress Engineering, and Advanced Node Evolution
The contact etch stop layer, commonly abbreviated as CESL, is a thin silicon nitride film deposited conformally over the transistor gate stack and source/drain regions before…
EKC Post-Etch Residue Removal: Principles, Mechanisms, and Advanced Node Integration in Semiconductor Manufacturing
In semiconductor manufacturing, every plasma etch step that defines a pattern also leaves behind unwanted byproducts on the wafer surface.
Etch Stop Layer (ESL) in Semiconductor Manufacturing: Principles, Physics, and Integration Logic
An etch stop layer (ESL) is a thin, selectively etch-resistant film deposited within a semiconductor device stack to terminate etching processes at precisely defined material…
Etch Rate: Removal, Selectivity, and Uniformity
Etch rate measures removal of a specified material over time. Learn why selectivity, location and feature shape change how the number should be read, then locate two STI etches in a public Flow.
Reactive Ion Etching (RIE): Physics, Mechanisms, and Evolution in Semiconductor Manufacturing
Reactive ion etching (RIE) is a dry etching technique that combines chemically reactive plasma species with directional ion bombardment to achieve highly anisotropic material…
Oxide Notch Etch in Semiconductor Manufacturing: Principles, Mechanisms, and Integration
Oxide notch etch selectively recesses oxide in some three-dimensional transistor flows. The exposed fin geometry may change gate control and current; the available 7nm course route is an overview, not a named notch step.
Demystifying Contact Hole Etch: Process Physics, Integration Principles, and Advanced Node Challenges
The fabrication of modern integrated circuits is divided into distinct manufacturing phases, where the transition between the active device layer and the metal routing network…
Wet Chemical Cleaning in BEOL: Principles and Mechanisms of EKC Post-Etch Residue Removal
In modern ultra-large-scale integration (ULSI) semiconductor manufacturing, defining features at advanced microelectronic scales requires precise execution across lithography…
Fundamentals of Tapered Profile Etch in Semiconductor Fabrication: Principles, Mechanisms, and Integration
Tapered profile etch, often referred to as slope etch or tapered etch, is a specialized dry etching technique designed to fabricate features with controlled, non-vertical…
Principles and Integration of Break-Through Etch in Advanced Semiconductor Manufacturing
In advanced semiconductor fabrication, achieving nanometer-scale structural precision requires absolute control over film interfaces and surface layers.