SemiFlows
FlowsChatAdvantagesPricingFAQAboutBlog

SemiFlows

Semiconductor process knowledge — flow visualization + Flow-aware, evidence-linked Q&A

FlowsFlow ChatAdvantagesPricingAboutFAQBlogConceptsContact Us

© 2026 SemiFlows. All rights reserved.

Terms of ServiceRefund PolicyPrivacy Policysupport@semiflows.comPayments by Paddle.com
SemiFlows
FlowsChatAdvantagesPricingFAQAboutBlog

Deep dive into plasma etching, wet etching, and pattern transfer physics. Learn about ion-assisted chemical reactions, selectivity mechanisms, and profile control principles from planar to FinFET architectures.

19 articles
reactive ion etching (RIE)etch ratecontact etch stop layer (CESL)etch stop layer (ESL)EKC post-etch residue removal (EKC)oxide notch etch

Related Process Flows

7nm FinFET7nm714 steps14nm FinFET14nm362 steps28nm Planar Flow28nm266 steps

Technical Blog

Deep dive into the physics and integration logic of semiconductor manufacturing

EtchingJul 4, 20265 min read

Reactive Ion Etching (RIE): Physics, Mechanisms, and Evolution in Semiconductor Manufacturing

Introduction Reactive ion etching (RIE) is a dry etching technique that combines chemically reactive plasma species with directional ion bombardment to achieve

EtchingJul 4, 20265 min read

Etch Rate in Semiconductor Manufacturing: Physical Principles, Process Dynamics, and Advanced Node Evolution

Introduction Etch rate — the volume or depth of material removed per unit time — is one of the most fundamental metrics in semiconductor fabrication, directly g

EtchingJul 4, 20265 min read

Contact Etch Stop Layer (CESL): Principles, Stress Engineering, and Advanced Node Evolution

Introduction The contact etch stop layer, commonly abbreviated as CESL, is a thin silicon nitride film deposited conformally over the transistor gate stack and

EtchingJul 4, 20265 min read

Etch Stop Layer (ESL) in Semiconductor Manufacturing: Principles, Physics, and Integration Logic

Introduction An etch stop layer (ESL) is a thin, selectively etch-resistant film deposited within a semiconductor device stack to terminate etching processes at

EtchingJul 4, 20265 min read

EKC Post-Etch Residue Removal: Principles, Mechanisms, and Advanced Node Integration in Semiconductor Manufacturing

Introduction In semiconductor manufacturing, every plasma etch step that defines a pattern also leaves behind unwanted byproducts on the wafer surface T2. These

EtchingJun 27, 20265 min read

Mastering the Oxide Notch Etch: Principles, Mechanisms, and Advanced Node Integration

Introduction In the pursuit of continuous transistor scaling, the semiconductor industry has transitioned from classic two-dimensional planar architectures to c

EtchingJun 1, 20265 min read

Fundamentals of Tapered Profile Etch in Semiconductor Fabrication: Principles, Mechanisms, and Integration

Introduction Tapered profile etch, often referred to as slope etch or tapered etch, is a specialized plasma etching technique designed to fabricate features wit

EtchingJun 1, 20265 min read

Demystifying Contact Hole Etch: Process Physics, Integration Principles, and Advanced Node Challenges

Introduction The fabrication of modern integrated circuits is divided into distinct manufacturing phases, where the transition between the active device layer a

EtchingJun 1, 20265 min read

Wet Chemical Cleaning in BEOL: The Science and Engineering of EKC Post-Etch Residue Removal

1. Introduction In modern ultra-large-scale integration (ULSI) semiconductor manufacturing, defining features at sub-nanometer scales requires an intricate danc

EtchingMay 31, 20265 min read

The Principles and Integration of Break-Through Etch in Advanced Semiconductor Manufacturing

Introduction In the field of advanced semiconductor fabrication, achieving sub-nanometer structural precision requires absolute control over every interface and

EtchingMay 31, 20265 min read

Remote Plasma Oxide Etch: Physical Mechanisms, Process Principles, and Advanced Node Integration

Introduction In advanced semiconductor manufacturing, the ability to selectively remove ultra-thin films without damaging the underlying atomic layers is a crit

EtchingMay 30, 20265 min read

Understanding Litho-Etch-Litho-Etch (LELE): Physical Principles, Process Integration, and Advanced Node Evolution

Introduction In the continuous pursuit of scaling down silicon integrated circuit (IC) features, semiconductor manufacturing eventually encountered the fundamen

1 / 2Next

SemiFlows

Semiconductor process knowledge — flow visualization + Flow-aware, evidence-linked Q&A

FlowsFlow ChatAdvantagesPricingAboutFAQBlogConceptsContact Us

© 2026 SemiFlows. All rights reserved.

Terms of ServiceRefund PolicyPrivacy Policysupport@semiflows.comPayments by Paddle.com
AllDepositionEtchingLithographyCMPIon ImplantationProcess IntegrationMaterialsInterconnectDevice PhysicsThermal Processing