Introduction
In the field of advanced semiconductor fabrication, achieving sub-nanometer structural precision requires absolute control over every interface and thin-film surface . One of the most critical yet frequently overlooked phases of plasma-based dry etching is the initial step: the break-through etch, also known as the breakthrough etch, BT etch, or initial etch .
Before the primary target material (such as polycrystalline silicon, metals, or advanced dielectrics) can be patterned, it must be cleared of any surface native oxide or organic residues . When silicon or metallic substrates are exposed to atmospheric oxygen or cleanroom humidity, they spontaneously react to form a highly stable, non-uniform native oxide layer, such as silicon dioxide (SiO2) . Because the main etch chemistries are intentionally engineered to possess extremely high selectivity against oxides to protect underlying stop layers, these chemistries are inherently inefficient at removing this initial native barrier , .
Without a dedicated initial etch step to uniformize and remove this native oxide, the subsequent main etch will suffer from extreme micro-loading, severe etch rate non-uniformity, and micromasking , (Engineering Practice). Consequently, the break-through etch acts as the gateway process that establishes the baseline uniformity and profile control for all subsequent structural pattern transfers in modern integrated circuits (ICs) , .
Process map
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Physics & Mechanism
Chemical Bond Dissociation and Sputter Thresholds
The physical and chemical principles of a break-through etch are rooted in chemical bond dissociation energies and ion-surface kinetics , . In a standard main etch step—such as the anisotropic etching of a polysilicon gate using hydrobromic acid/oxygen (HBr/O2) chemistry—the process is designed to rely heavily on chemical reactions that form volatile silicon tetrabromide (SiBr4) , . However, the bond energy of a silicon-oxygen (Si-O) bond in native oxide is approximately 8.3 eV, whereas the silicon-silicon (Si-Si) bond energy is only around 3.4 eV . Halogen radicals (like Bromine or Chlorine) generated in the plasma cannot spontaneously break the highly stable Si-O network under typical chemical etching conditions .
To overcome this thermodynamic barrier, the BT etch must temporarily lower the selectivity towards oxides . This is achieved by transitioning the plasma mechanism from a chemically dominated regime to a mixed physical-chemical or highly physical regime , . In reactive ion etching (RIE) systems, this is accomplished by using fluorine-containing gases such as tetrafluoromethane (CF4) or by significantly increasing the radio frequency (RF) bias power to elevate the physical sputtering component .
Ion-Assisted Surface Reactions
When CF4 is introduced during the BT etch, the plasma generates active fluorine (F) radicals and fluorocarbon ions (CFx+) . The fluorine species chemically react with the native oxide to form volatile silicon tetrafluoride (SiF4) gas, while concurrent ion bombardment mechanically weakens the oxide lattice , . The synergetic interaction between physical sputtering and chemical volatilization is described by the ion-assisted chemical etching model, where the physical bombardment of ions provides the activation energy necessary for the chemical reaction to proceed rapidly , (Engineering Practice).
This mechanism contrasts with wet chemical etching, where interfacial mass transport and diffusion boundary layers dictate chemical dissolution rates . In dry plasma BT etching, the directional flux of accelerated ions ensures that the native oxide is removed with high anisotropy, preserving the vertical profile of the masking layer , .
Process Principles
To achieve an optimal break-through etch, engineers must carefully balance multiple plasma parameters . Because the BT step lasts only a short duration (typically a few seconds), the rate of change and directional impact of these parameters must be tightly controlled .
- RF Source Power: The source power controls the overall plasma density and radical generation rate within the chamber . High source power ensures a steady flux of reactive radicals, but must be balanced to avoid premature mask erosion .
- RF Bias Power: The bias power regulates the potential difference between the plasma bulk and the wafer electrostatic chuck, directly determining the kinetic energy of the incoming ions , . During a BT etch, a higher RF bias power is typically applied compared to the main etch, maximizing physical sputtering to rupture the stable native oxide bonds .
- Gas Chemistry Composition: The addition of fluorine-rich precursors (e (Engineering Practice).g., CF4 or sulfur hexafluoride (SF6)) is critical during the initial etch . Once the native oxide is breached, the chemistry is quickly switched back to more selective halogen mixtures (e (Engineering Practice).g., HBr/O2 or Cl2/Ar) to prevent isotropic lateral etching of the underlying silicon substrate , .
- Chamber Pressure: Lowering the chamber pressure increases the mean free path of the ions, reducing ion-neutral scattering and resulting in a highly directional, perpendicular ion flux , (Engineering Practice). This directional bombardment is essential for achieving anisotropic native oxide removal in deep, high-aspect-ratio trenches .
- Substrate Temperature: Electrode temperature alters the desorption rates of volatile byproducts and affects polymer deposition kinetics on the feature sidewalls , . Precise thermal regulation prevents the formation of non-volatile residue during the transition from the BT step to the main etch .
Challenges & Failure Modes
Implementing a robust break-through etch is highly challenging due to the narrow process window and the competing demands of oxide removal versus substrate protection . Several critical failure modes can occur if the BT step is poorly optimized:
Micromasking and Silicon 'Grass'
If the breakthrough etch step is too short, or if the ion energy is insufficient to completely clear the native oxide across the entire wafer, micro-islands of native oxide will remain , (Engineering Practice). During the subsequent main etch, these residual oxide patches act as unexpected, highly robust masks because the main etch chemistry has high selectivity against oxides . This leads to a severe defect known as micromasking, resulting in unetched pillars or grass-like structures of target material that cause electrical shorts , (Engineering Practice).
Punch-Through and Under-layer Damage
Conversely, if the BT etch is excessively aggressive, long, or utilizes too high of an RF bias power, it can punch through thin underlying layers , . In advanced logic structures, the gate dielectric (such as silicon dioxide or a high-k dielectric) beneath the polysilicon or metal gate is extremely thin , . An over-extended BT step will easily erode this thin barrier, damaging the active channel, causing direct structural deformation, and inducing catastrophic dielectric breakdown or high leakage currents , (Engineering Practice).
Critical Dimension Skew and Photoresist Erosion
Highly physical sputtering during the initial etch step degrades the selectivity of the process relative to the organic photoresist mask , . If the resist is significantly eroded or faceted at the pattern edges, this geometric distortion is transferred into the underlying film , . This results in a massive critical dimension (CD) skew—the difference between the after development inspection (ADI) CD and the after cleaning inspection (ACI) CD .
Dielectric Residue and Polymerization
In complex contact etching, maintaining a balance between polymerization and volatilization is critical , . Insufficient physical bias or incorrect chemistry during the initial opening can result in dielectric residue or incomplete clearing of the contact hole bottom . This residue acts as an electrical insulator, leading to an open-circuit failure or unacceptably high contact resistance .
Technology Node Evolution
The integration and complexity of the break-through etch have evolved dramatically alongside the scaling of CMOS devices .
[Technology Node Scaling Trend]
28nm Planar 14nm FinFET 7nm & Beyond (GAA)
+--------------+ +--------------+ +--------------+
| Planar Poly | =====> | 3D Fin RIE | =====> | Atomic Layer |
| HBr/O2/CF4 | | High Aspect | | Etch (ALE) |
+--------------+ +--------------+ +--------------+
28nm Planar Node
During the planar era, exemplified by the 28nm Planar Flow, gate patterning primarily involved traditional planar polysilicon stacks , . The native oxide layer on the flat polysilicon surface was relatively uniform . A short, simple RIE breakthrough step using a mixture of CF4 and Cl2/Ar with moderate bias power was sufficient to clear the oxide without risking gate oxide punch-through , (Engineering Practice).
14nm FinFET Node
The transition to the 3D fin field effect transistor architecture at the 14nm FinFET node significantly complicated the BT etch . The 3D topography introduced highly non-uniform native oxide coverage , (Engineering Practice). Because the native oxide thickness varied between the top of the fins and the deep trench bottom, a standard planar breakthrough step would severely over-etch and damage the top of the silicon fins before clearing the trenches , (Engineering Practice). To resolve this, engineers adopted advanced "soft landing" initial etches , using multi-step bias ramping and highly selective fluorocarbon ratios to clear the native oxide uniformly without damaging the 3-dimensional silicon geometries.
7nm Node and Beyond
At the 7nm FinFET node and beyond, the introduction of the high-k metal gate (HKMG) stack altered the material landscape . Instead of just clearing native silicon dioxide, the BT etch had to break through native oxides of transition metals (such as Titanium oxide or Tantalum oxide) and complex high-k dielectrics , (Engineering Practice). This required the incorporation of high-temperature plasma processes and atomic layer etching (ALE) schemes to achieve sub-angstrom depth control, preventing any degradation of the active multi-gate structures while maintaining low parasitic contact resistance .
Related Processes
The performance and process window of the break-through etch are heavily coupled with both upstream and downstream process steps , , .
Lithography
The photolithography step, particularly when using extreme ultraviolet lithography, dictates the initial dimensions and thickness of the photoresist mask , (Engineering Practice). Because advanced lithography utilizes ultra-thin photoresists to prevent pattern collapse, the BT etch must be engineered with maximum anisotropy and minimum physical sputtering time to prevent the plasma from completely consuming the thin resist mask , (Engineering Practice).
Surface Cleaning and Queue-Time Control
Prior to entering the dry etch chamber, wafers typically undergo a wet chemical cleaning process (such as dilute hydrofluoric acid) to remove the bulk of the native oxide . However, because silicon surfaces are highly reactive, native oxide begins to reform immediately upon exposure to air . Therefore, strict queue-time (Q-time) controls are enforced between the pre-clean and the dry etch loading to ensure a consistent, thin native oxide starting point , (Engineering Practice).
Metallization and Contact Formation
Following the contact via etching, which requires highly selective breakthrough and main etch steps , the contact must be filled with conductive metals . In advanced metallization, the quality of the BT etch directly determines the interfacial resistance . If any dielectric residue or oxide remains at the bottom of the contact via, it can prevent proper nucleation of the barrier layers, causing metal fill voids , or dramatically increase the contact resistance .
Future Outlook
As the semiconductor industry transitions from FinFETs to nanosheet Gate-All-Around (GAA) architectures and forks toward 2D transition metal dichalcogenides (TMDs), traditional physical sputtering-based break-through etches are reaching their physical limits . Future manufacturing nodes will increasingly rely on two key technologies:
1 (Engineering Practice). Atomic Layer Etching (ALE): By decoupling the chemical adsorption and physical desorption phases, ALE enables the removal of native oxides monolayer-by-monolayer with virtually zero physical damage to the underlying active channel, ensuring perfect selectivity and pattern fidelity . 2. Dry Chemical Surface Conditioning: Integrated remote-plasma chemical dry cleans (such as nitrogen trifluoride (NF3) and ammonia (NH3) vapor-phase reactions) are being integrated directly into vacuum clusters . These processes chemically volatilize native oxides isotropically and with zero ion-bombardment damage, allowing a completely "zero-bias" breakthrough step prior to main etch and subsequent atomic layer deposition (ALD) or metallization steps .