Principles and Integration of Break-Through Etch in Advanced Semiconductor Manufacturing

Introduction

In advanced semiconductor fabrication, achieving nanometer-scale structural precision requires absolute control over film interfaces and surface layers. One of the most critical initial phases of plasma-based dry etching is the break-through etch, also referred to as the breakthrough etch, BT etch, or initial etch step.

Before a primary target material—such as polycrystalline silicon, metals, or dielectrics—can be patterned, its surface must be cleared of native oxide or organic residues. When silicon or metallic substrates are exposed to ambient cleanroom environments, they spontaneously react to form a thin, stable, and often non-uniform native oxide layer, such as silicon dioxide (SiO2). Because main etch chemistries are intentionally engineered to possess high selectivity against oxides to protect underlying etch stop layers, these chemistries are inherently inefficient at removing this initial native barrier.

Without a dedicated initial etch step to uniformize and remove this native oxide, the subsequent main etch suffers from severe micro-loading, etch rate non-uniformity, and localized masking effects. Consequently, the break-through etch acts as a prerequisite step that establishes baseline surface uniformity and profile control for subsequent structural pattern transfers in modern integrated circuits.

Physics & Mechanism

Chemical Bond Dissociation and Sputter Thresholds

The physical and chemical principles of a break-through etch are rooted in chemical bond dissociation energies and ion-surface kinetics. In a standard main etch step—such as the anisotropic etching of a polysilicon gate using hydrobromic acid/oxygen (HBr/O2) chemistry—the process relies heavily on chemical reactions that form volatile silicon tetrabromide (SiBr4). However, the bond energy of a silicon-oxygen (Si-O) bond in native oxide is substantially higher than that of a silicon-silicon (Si-Si) bond. Halogen radicals generated in the plasma cannot spontaneously break the highly stable Si-O network under chemical etching conditions alone.

To overcome this thermodynamic barrier, the BT etch temporarily alters the process regime toward higher physical ion action. A more physical etching regime enhances directionality for profile control, but typically trades off material selectivity compared to a purely chemical process [T1]. In reactive ion etching (RIE) systems, this is accomplished by introducing fluorine-containing gases such as tetrafluoromethane (CF4) or by increasing the radio frequency (RF) bias power to elevate physical sputtering.

Ion-Assisted Surface Reactions

When CF4 is introduced during the BT etch, the plasma generates active fluorine (F) radicals and fluorocarbon ions (CFx+). The fluorine species chemically react with native oxide to form volatile silicon tetrafluoride (SiF4) gas, while concurrent ion bombardment mechanically weakens the oxide lattice. The synergetic interaction between physical sputtering and chemical volatilization is described by the ion-assisted chemical etching model, where physical bombardment provides the activation energy necessary for chemical reaction to proceed.

In dry plasma BT etching, the directional flux of accelerated ions ensures that native oxide is removed with anisotropic control, preserving the vertical profile of the masking layer.

Process Principles

To achieve an optimal break-through etch, process engineers balance multiple plasma parameters over a brief duration:

• RF Source Power: Controls overall plasma density and radical generation. Sufficient source power ensures a steady flux of reactive radicals without inducing excessive mask erosion.
• RF Bias Power: Regulates the potential difference across the plasma sheath, directly determining incoming ion kinetic energy. Higher RF bias power is applied during BT etching compared to main etching to break stable surface bonds through ion sputtering.
• Gas Chemistry Composition: Fluorine-rich precursors (such as CF4 or SF6) break through the native oxide. Once breached, chemistry transitions to selective mixtures (such as HBr/O2 or Cl2/Ar) to minimize lateral loss of underlying layers.
• Chamber Pressure: Operating at lower chamber pressure increases the ion mean free path, reducing scattering and yielding a directional, perpendicular ion flux for clearing high-aspect-ratio features.
• Substrate Temperature: Controls byproduct desorption and polymer deposition rates on sidewalls, preventing non-volatile residue formation during the transition to main etch.

Challenges & Failure Modes

Implementing a robust break-through etch involves operating within a narrow process window due to competing demands between native oxide removal and substrate preservation:

Micromasking and Non-Uniform Profiles

If the break-through etch duration is insufficient or ion energy is inadequate, micro-islands of native oxide remain. Incomplete removal or surface mask issues during initial etching steps can lead to micromasking, resulting in increased surface roughness and non-uniform patterning [P1]. During the subsequent main etch, these residual oxide patches act as unexpected masks, causing unetched micro-pillars that lead to structural defects or electrical shorting.

Punch-Through and Under-layer Damage

Conversely, an overly aggressive BT etch with excessive RF bias power can punch through thin underlying layers. In advanced logic structures, the gate dielectric beneath a conductive gate layer is extremely thin. An over-extended BT step can erode this thin dielectric barrier, damaging the channel region and leading to elevated gate leakage or threshold voltage instability.

Critical Dimension Skew and Photoresist Erosion

Strong physical sputtering during the initial etch step degrades mask selectivity against organic photoresists. If photoresist corners are eroded or faceted, the geometric distortion transfers into the underlying film, causing critical dimension (CD) skew between post-lithography and post-etch inspection.

Dielectric Residue

In contact and via etching, insufficient physical bias or improper chemistry balance can leave dielectric residues at feature bottoms. Unremoved residual oxides increase contact resistance or prevent uniform barrier layer nucleation.

Technology Node Evolution

The integration and complexity of the break-through etch have evolved alongside device scaling:

Planar CMOS Nodes

In planar transistor architectures, gate patterning primarily involved planar polysilicon stacks on flat substrates. Native oxide layers were relatively uniform across the wafer. A short RIE breakthrough step using mixtures of CF4 and Cl2/Ar with moderate bias power was sufficient to clear native oxide prior to main etching.

FinFET Architecture

The transition to 3D fin field effect transistor architectures introduced non-uniform native oxide formation across vertical fin tops and deep trench sidewalls. Standard planar breakthrough steps risk over-etching fin tops before clearing trench bottoms. Process implementations adopted stepped bias ramping and tailored fluorocarbon ratios to clear native oxide across 3D topologies without excessive recess damage.

Advanced HKMG and Gate-All-Around

With high-k metal gate (HKMG) and nanosheet Gate-All-Around (GAA) structures, BT etching must address native oxides of transition metals and complex dielectrics. This requires atomic layer etching (ALE) schemes and precise energy control to maintain interface quality while preventing channel degradation.

Related Processes

Lithography

Photolithography, particularly with extreme ultraviolet (EUV) light, defines thin photoresist features. Because EUV resists are thin to prevent pattern collapse, the BT etch must be optimized to minimize resist consumption while providing anisotropic native oxide removal.

Surface Cleaning and Queue-Time Control

Prior to entering dry etch chambers, wafers undergo wet chemical pre-cleans (such as dilute HF) to remove bulk oxides. Because exposed silicon re-oxidizes in air, strict queue-time (Q-time) controls are enforced between pre-clean and dry etch loading to maintain consistent native oxide starting thickness.

Metallization and Contact Formation

Following contact opening, conductive metals are deposited. The quality of the BT etch at the contact interface determines contact resistance and ensures void-free barrier deposition.

Future Outlook

As device dimensions approach physical scaling limits, conventional sputtering-based break-through etches face strict damage budgets. Self-arresting etch mechanisms allow highly controlled pattern transfer at nanoscale dimensions without relying entirely on strict timing control [P2]. Future nodes increasingly leverage two advanced approaches:

1. Atomic Layer Etching (ALE): Decouples chemical adsorption and physical desorption phases to remove oxides monolayer-by-monolayer with minimal physical damage to underlying channels.
2. Dry Chemical Surface Conditioning: Integrated remote-plasma chemical cleans (such as NF3/NH3 vapor reactions) chemically volatilize native oxides in vacuum integrated clusters, enabling low-damage surface preparation prior to main etching and subsequent atomic layer deposition (ALD) or metallization.