Introduction
In the pursuit of continuous transistor scaling, the semiconductor industry has transitioned from classic two-dimensional planar architectures to complex three-dimensional non-planar architectures, such as the vertical fin-based field-effect transistor (FinFET) [P1, P2]. This architectural shift fundamentally altered how isolation and active device dimensions are defined . In planar technologies, device isolation was achieved by filling trenches with silicon dioxide ($SiO_2$) and planarizing them flat with the active silicon surface . In non-planar architectures, however, the gate must wrap around a portion of the vertical silicon fin to establish electrostatic control [P2, T2].
This 3D construction requires a dedicated process known as the fin reveal etch or shallow trench isolation (STI) recess [P1, P2]. The oxide notch etch (often associated with creating a localized STI notch at the fin base) is the critical wet or dry etching step designed to selectively recess the isolation oxide relative to the silicon fin and its protecting hard mask layers [P1, A1].
The precision of this recess step directly determines the exposed vertical fin height, which represents the effective channel width of the transistor [P1, P2]. Any variation in this height directly cascades into major electrical deviations, including shifts in threshold voltage ($V_{th}$) and subthreshold swing [P2, T3]. Consequently, understanding the underlying physics, chemical kinetics, and process integration parameters of the oxide notch etch is vital for senior process engineers and integration specialists in advanced semiconductor manufacturing .
Physics & Chemical Mechanisms of Oxide Notch Etch
Transistor Electrostatics and Channel Width Definition
The physical necessity of the oxide notch etch is rooted in the electrostatic control of non-planar devices . According to Poisson's equation, when a gate electrode wraps around multiple sides of a thin silicon channel, the depletion regions from opposing gates overlap, suppressing short-channel effects and reducing drain-induced barrier lowering (DIBL) [P2, T2]. The active channel height is defined by the depth of the STI recess .
Because the subthreshold current of a modern transistor scales exponentially with the gate voltage, minor variations in the exposed gate perimeter can lead to vast differences in off-state leakage current ($I_{off}$) . A deeper oxide notch etch increases the effective channel width, thereby raising the on-state drive current ($I_{on}$) but potentially exposing the channel to punch-through leakage at the fin base . Conversely, an under-etched STI recess reduces the active channel height, degrading $I_{on}$ and shifting $V_{th}$ upwards [P2, T3].
Wet Etch Chemistry and Reaction Kinetics
The most common chemical approach for the oxide notch etch is isotropic wet etching using hydrofluoric acid (HF) based formulations, typically dilute hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF) [P1, P2]. The basic chemical mechanism involves the nucleophilic attack of fluoride species on the silicon-oxygen bonds:
$$\text{SiO}_2 + 6\text{HF} \rightarrow \text{H}_2\text{SiF}_6 + 2\text{H}_2\text{O}$$
In BHF, ammonium fluoride ($NH_4F$) is added as a buffering agent to maintain a constant concentration of the active etching species ($HF_2^-$ and $HF$), stabilizing the etch rate over time .
FCVD Oxide Material Dependencies
In modern advanced nodes, the extremely tight pitch between vertical fins makes traditional high-density plasma CVD methods prone to forming voids [P1, P2]. To address this, flowable chemical vapor deposition (FCVD) oxide has been introduced to achieve void-free oxide filling . However, the initial as-deposited FCVD oxide consists of a low-density, metastable amorphous network containing incomplete reaction products, such as $Si-N$ and $Si-OH$ species .
To convert this metastable film into high-quality $SiO_2$, the film must undergo post-deposition treatments, including ozone ($O_3$) curing, ultraviolet (UV) curing, and steam annealing . Prior to the final steam anneal, the cured film continues to age in ambient room air, absorbing moisture and oxygen to promote network rearrangement .
Quantitative analysis using electron energy loss spectroscopy (EELS) combined with scanning transmission electron microscopy (STEM) has revealed that incomplete conversion leaves nitrogen-rich "bubble" regions containing elevated levels of nitrogen . These low-density, nitrogen-rich regions exhibit a significantly accelerated wet etch rate during the subsequent BHF notch process, leading to severe non-uniformity and erratic fin heights across the chip .
[Unconverted FCVD Oxide] ──(O3/UV Cure + Ambient Aging)──> [Denser SiO2 Network]
│ │
▼ (No Aging) ▼
[N-Rich "Bubble" Regions] [Uniform Dry/Wet Etch]
│ │
▼ (BHF Etch) ▼
[Accelerated Local Etching] [Precise Fin Reveal]
Process Principles and Parameter Interactions
To achieve high-yield device integration, process engineers must manipulate several key parameters to control the etch front directionally and selectively .
Material Conversion and Etch Rate Modulations
The quality of the filled oxide acts as a primary lever for controlling the wet etch rate [P1, P2]. A fully converted and densified oxide network exhibits a lower, more predictable wet etch rate than a poorly cured film [P1, P2].
If the thermal budget of the overall integration flow limits high-temperature steam annealing (to prevent unwanted dopant diffusion), the resulting lower-quality oxide will have an elevated etch rate . To moderate this high etch rate and recover a controllable process window, engineers must either decrease the concentration of the active HF species in the bath or shorten the etching time . Reducing the chemical concentration is generally preferred because it provides a wider, more stable process window compared to highly sensitive, short-duration etch recipes .
Aging Time Dynamics
The duration of ambient air aging between the initial curing (UV or ozone) and the final high-temperature steam anneal plays a decisive role in the final etch performance . Quantitative EELS profiling demonstrates that a specific minimum aging time is required to allow complete oxygen and water diffusion from the ambient atmosphere into the metastable FCVD film .
When the film is aged sufficiently, the nitrogen content drops close to zero, and the local density stabilizes . This stabilization ensures that the subsequent wet BHF etch proceeds with uniform isotropic front propagation, eliminating the localized "bubble" etching effects that lead to severe across-chip fin height variations .
Dry vs. Wet Etch Integration Loading
Process engineers must continuously balance the trade-offs between dry and wet etching technologies (Engineering Practice). Dry etching techniques, such as reactive ion etching (RIE), offer highly anisotropic profiles but are plagued by severe across-chip loading effects [P1, T1]. Because the local pattern density varies across the die, the flux of reactive ions and neutral radicals during dry etching differs, resulting in non-uniform oxide recess depths .
Wet etching using BHF, conversely, is not subject to these micro-loading effects and yields superior across-chip variability control . However, because wet chemical etching is inherently isotropic, it is highly prone to lateral undercutting and structural modifications at the fin base .
Challenges and Failure Modes
The execution of an oxide notch etch is fraught with physical and chemical failure modes that can completely destroy device yields if not managed properly .
Isotropic Footing and Under-Etching
Because wet HF etching is isotropic, the chemical solution etches both vertically and horizontally at the same rate . This isotropic nature typically results in a residual "foot" of oxide at the bottom edge of the silicon fin, a phenomenon known as STI footing .
If the footing is too pronounced, it prevents the gate electrode from fully wrapping around the base of the channel, restricting the effective gate perimeter and causing a localized degradation of electrostatic control [P2, T3]. Conversely, if the process is over-extended to eliminate the footing, the lateral undercut can progress too deep, creating a severe STI notch that exposes the sub-fin region [P1, P2].
Isotropic Wet Etch With SiN Barrier Liner
(Silicon Fin) (Silicon Fin)
│ │ │ │
======┴===┴====== ======┴===┴======
░░░░░░\ /░░░░░ | SiN | | SiN |
░░░░░░░\___/░░░░░░ |_____|_____|_____
(STI Oxide Foot) (Stabilized Base)
SiGe Fin Base Oxidation and Lifting
In advanced high-performance nodes, silicon-germanium (SiGe) is introduced in the channel region to induce compressive strain and boost hole mobility . However, SiGe is highly sensitive to oxidative environments . During subsequent high-temperature annealing or oxidation processes, oxygen can readily diffuse from the adjacent buried oxide (BOX) or STI oxide directly into the bottom corners of the SiGe fin [A1, A2].
This selective oxidation at the fin root leads to a massive non-uniform volumetric expansion as the SiGe is converted to SiGe-oxide [A1, A2]. This expansion triggers strain relaxation, introduces lattice dislocation defects, and can cause the entire fin structure to lift, deform, or completely collapse [A1, A2].
To prevent this catastrophic failure, an ultrathin, conformal silicon nitride (SiN) liner must be deposited prior to the oxide fill to serve as an oxygen diffusion barrier [A1, A2]. The oxide recess process must then be carefully designed not to strip or breach this protective SiN liner [A1, A2].
Fin Pulling and Capillary Collapse
Following a deep oxide notch etch or wet etching fin reveal step, the extremely high-aspect-ratio silicon fins are left standing unsupported in the wet chemical bath . During the subsequent DI water rinsing and drying phases, the surface tension of the evaporating liquid exerts immense capillary forces between adjacent fins (Engineering Practice).
If the STI recess is too deep, the structural support at the fin base is compromised, and the capillary pressure will pull adjacent fins together, causing them to bend, stick (stiction), or break off at the base (Engineering Practice). This failure mode requires the integration of specialized supercritical $CO_2$ drying or highly optimized isopropyl alcohol (IPA) surface-tension-reducing drying systems (Engineering Practice).
Technology Node Evolution: From 28nm Planar to Advanced FinFETs
The role and complexity of the oxide recess have evolved dramatically across successive technology nodes .
The 28nm Planar Node
In the 28nm planar node (e (Engineering Practice).g., 28nm Planar Flow), device isolation was achieved using planar STI structures . The oxide was filled, planarized using chemical mechanical planarization (CMP), and remained flush with the silicon substrate active area . No fin reveal or oxide notch etch was required because the transistor channel remained entirely two-dimensional on the surface of the wafer [T1, P2].
The 14nm FinFET Node
With the transition to the 14nm FinFET node (e .g., 14nm FinFET), the transistor architecture became fully three-dimensional . This shift introduced the absolute necessity of the fin reveal wet etch using BHF or DHF to expose the vertical walls of the silicon fins [P1, P2].
To optimize this node, alternative designs such as scallop-shaped FinFETs (S-FinFETs) were proposed on bulk silicon substrates . These devices utilized a multi-step, Bosch-like dry etch sequence consisting of alternating passivation and isotropic silicon etching to create scalloped sidewalls with a "bulged body and narrow neck" geometry . This specialized shape allowed the metal gate to wrap around the narrow neck, achieving a quasi-surrounding-gate effect that mimicked a nanowire and drastically suppressed DIBL and subthreshold swing degradation .
The 7nm Node and Beyond
At the 7nm FinFET node (e .g., 7nm FinFET), fin pitches shrunk to sub-30nm dimensions, and fin aspect ratios skyrocketed . Traditional isotropic wet chemical etching faced severe limitations due to capillary-induced fin collapse and layout-dependent loading [P2, (Engineering Practice)].
This forced the industry to adopt dry, highly selective isotropic etching technologies, such as remote plasma oxide etch or quasi-atomic layer etching (ALE) schemes [P2, (Engineering Practice)]. These advanced dry processes use cyclic gas-phase chemistries to remove the oxide monolayer-by-monolayer, eliminating liquid surface tension and providing sub-nanometer control over the final STI recess depth [P2, (Engineering Practice)].
Related Process Steps and Integration Logic
The oxide notch etch does not occur in a vacuum; it is highly dependent on upstream processes and directly impacts downstream modules .
[STI Trench Etch & Nitride Mask]
│
▼
[FCVD Oxide Fill & O3/UV Cure]
│
▼
[Ambient Air Aging (10-15 hrs)] ────> [Prevents N-Rich Bubble Formation]
│
▼
[Steam Anneal Densification]
│
▼
[STI CMP & Hard Mask Strip]
│
▼
[Oxide Notch Etch (Fin Reveal)] ────> [Directly Defines Effective Fin Height]
│
▼
[PTS / Channel Implantation]
│
▼
[Dummy Gate Integration] ────> [Determines Channel Wrapping Performance]
Upstream Dependencies: CMP and Hard Mask Removal
Before the oxide notch etch can begin, the active fins are protected by a silicon nitride ($Si_3N_4$) hard mask, which is used to pattern the STI trenches . The trenches are filled with FCVD oxide and planarized using CMP, which is programmed to stop directly on the protective nitride mask [T1, A1].
Once planarization is complete, the nitride hard mask is stripped away (typically using hot phosphoric acid), exposing the top surfaces of the silicon fins [A1, T1]. This sequence leaves the STI oxide slightly proud of the fins, setting the stage for the selective oxide notch etch back .
Downstream Impact: Dummy Gate and HKMG Integration
After the oxide notch etch successfully reveals the vertical fin channels, a sacrificial dummy gate (typically made of amorphous silicon or polysilicon) is conformally deposited over the exposed fins . The height and uniformity of the revealed fin determine the topography that the dummy gate must conformally cover [P2, P3].
Any localized non-uniformity in the fin reveal height will cascade into variations in gate length, gate-edge roughness, and metal-gate filling capability during the subsequent replacement high-k/metal gate (HKMG) integration process [P2, P3]. If the gate metal fails to fill the tight gaps around a poorly recessed fin, it leads to severe effective work function fluctuations and device failure .
Channel Engineering and PTS Implantation
To prevent sub-surface leakage beneath the active channel, a punch-through stopping (PTS) implantation is performed [P2, P3]. This well-doping profile is carefully aligned with the base of the recessed STI oxide [P2, P3].
If the oxide notch etch is non-uniform, the physical location of the PTS implant relative to the bottom of the gate electrode will vary [P2, P3]. An over-etched STI recess may push the active gate below the heavily doped PTS region, degrading device mobility, while an under-etched recess may cause high leakage through the un-gated fin base [P2, P3].
Future Outlook and Emerging Paradigms
As the semiconductor roadmap transitions from FinFETs to gate-all-around (GAA) nanosheets and forksheets, the role of the oxide notch etch is undergoing further transformation [P2, (Engineering Practice)]. In nanosheet architectures, the vertical silicon fin is replaced by a stack of horizontal silicon nanosheets suspended in a sacrificial silicon-germanium matrix .
The primary isolation challenges shift from a simple vertical STI recess to the highly complex "inner spacer" cavity etching, which requires extreme lateral selectivity to recess the SiGe layers relative to the silicon sheets without attacking the surrounding dielectric oxides [P2, (Engineering Practice)].
Furthermore, the continuous integration of new high-mobility channel materials, such as indium gallium arsenide (InGaAs) or pure germanium, requires even more stringent chemical controls . Since these materials are highly sensitive to conventional acid mixtures, the industry is increasingly relying on anhydrous gas-phase chemistries and dry atomic-scale recess techniques to replace traditional wet chemical baths [P2, (Engineering Practice)].
Metrology tools must also keep pace; the continued use of advanced characterization methods, such as dual-EELS STEM, will remain essential to mapping atomic-scale composition and density variations in ultra-thin isolation structures to ensure uniform etching in sub-3nm regimes .