Remote Plasma Oxide Etch: Physical Mechanisms, Process Principles, and Advanced Node Integration

Introduction

In advanced semiconductor manufacturing, the ability to selectively remove ultra-thin films without damaging the underlying atomic layers is a critical requirement for device scaling [T2]. As transistors have transitioned from planar architectures to complex three-dimensional structures, conventional dry etching techniques have faced physical limitations [T1], [T2]. Standard reactive ion etching (RIE) systems subject the substrate to energetic ion bombardment, which can cause severe lattice defectivity, wafer charging, and loss of critical dimension (CD) control [T2], [P4].

To overcome these issues, remote plasma oxide etch technologies have emerged as indispensable tools [P2]. Unlike direct plasma systems where the wafer is in contact with the glow discharge, a remote plasma source (RPS) generates active chemical species upstream, delivering only neutral radicals to the wafer surface [T1], [P3]. This spatial separation eliminates physical sputtering damage, making remote plasma oxide etch highly isotropic, chemically selective, and physically gentle [P2], [P3].

Among these techniques, the SiCoNi (alternatively written as siconi) process is one of the most prominent dry chemical etching solutions used in advanced fabrication modules [A1]. Based on nitrogen trifluoride ($NF_3$) and ammonia ($NH_3$) chemistries, the siconi process selectively removes silicon dioxide ($SiO_2$) while leaving elemental silicon, silicon-germanium ($SiGe$), and silicon nitride ($Si_3N_4$) intact [A1]. Understanding the physical, chemical, and thermodynamic principles of remote plasma oxide etch is essential for engineers working on contemporary sub-10nm technology nodes [P3].

Physics & Mechanism

Spatial Separation and radical Transport

The fundamental design of a remote plasma system relies on decoupling the plasma generation zone from the wafer processing chamber [T1], [P3]. High-density plasma is ignited upstream using microwave (MW) or inductively coupled plasma (ICP) excitation [T1], [P1]. The plasma effluents then pass through a showerhead, a plenum, or a conductive grid electrode [P3], [A2].

This grid electrode is typically grounded, allowing it to act as an electrostatic shield that recombines or filters out charged particles (electrons and ions) while remaining permeable to neutral atoms, molecules, and radicals [A2]. Consequently, the downstream process chamber maintains an ion-free environment where the etch mechanism is driven entirely by thermal neutral chemistry [P3], [A2].

The SiCoNi Dry Chemical Etch Mechanism

In the widely used SiCoNi process, the remote plasma chemistry is sustained using a mixture of $NF_3$ and $NH_3$ gases [A1]. The chemical reaction proceeds via a distinct two-step mechanism:

1 (Engineering Practice). Low-Temperature Solid-State Reaction: The upstream plasma dissociates the reactant gases into active species, including ammonium fluoride ($NH_4F$) and ammonium hydrogen fluoride ($NH_4F\cdot HF$) complexes [P2]. These gaseous reactants flow downstream and adsorb onto the wafer surface at relatively low temperatures (Engineering Practice). They react selectively with the native or thermal silicon dioxide ($SiO_2$) layer to form solid ammonium hexafluorosilicate salt according to the following simplified reaction pathway:

$$\text{SiO}_2(s) + 6\text{NH}_4\text{F}(g) \rightarrow (\text{NH}_4)_2\text{SiF}_6(s) + 2\text{H}_2\text{O}(g) + 4\text{NH}_3(g)$$

This reaction is highly self-limiting because the solid reaction product, ammonium hexafluorosilicate $((\text{NH}_4)_2\text{SiF}_6)$, forms a diffusion barrier that eventually prevents further fresh reactants from reaching the unreacted $SiO_2$ interface beneath [P2].

2. Thermal Sublimation (Desorption): Once the solid-state reaction is complete, the wafer is heated to an elevated temperature (Engineering Practice). This thermal budget induces the decomposition and sublimation of the solid salt into volatile byproducts, which are pumped out of the chamber, exposing a pristine, clean surface [A1]:

$$(\text{NH}_4)_2\text{SiF}_6(s) \xrightarrow{\Delta} \text{SiF}_4(g) + 2\text{NH}_3(g) + 2\text{HF}(g)$$

NF3/O2 and NF3/N2/O2/H2 Alternative Chemistries

Beyond the $NF_3/NH_3$ system, other gas mixtures are employed for targeted selectivity. In an $NF_3/O_2$ remote plasma, the dissociation yields highly reactive fluorine ($F$) atoms alongside gas-phase nitric oxide ($NO$) [P1]. The $NO$ molecules preferentially adsorb onto nitrogen-containing films like silicon nitride ($Si_3N_4$), facilitating the depletion of surface nitrogen and accelerating the etch rate of nitride while leaving pure oxide relatively unaffected [P1].

Conversely, when hydrogen ($H_2$) is introduced to form an $NF_3/N_2/O_2/H_2$ discharge, the interaction produces vibrationally excited hydrogen fluoride ($HF^*$) [P2]. This vibrationally excited species possesses localized energy that significantly lowers the chemical reaction barrier on $Si_3N_4$ surfaces, allowing highly selective isotropic etching of nitride over $SiO_2$ even without physical ion bombardment [P2].

Process Principles

To achieve precise etch control, process engineers must manipulate several key parameters, each exerting a directional influence on the process outcomes [T2].

RF Power and Radical Flux

Increasing the radio frequency (RF) or microwave power applied to the remote plasma source increases the dissociation rate of the precursor gases [T1], [P1]. This leads to an increased density of fluorine atoms and reactive radicals flowing downstream, which directionally increases the etch rate [P1], [P3]. However, excessively high power density can increase the gas temperature within the source, promoting parasitic endothermic reactions or raising the plasma potential, which increases the risk of ion leakage through the filtering grid [P3].

Gas Flow Ratios

The ratio of the feed gases directly dictates the chemistry at the wafer surface [T2]. In the siconi chemistry, the ratio of $NH_3$ to $NF_3$ must be carefully balanced [P1]. An excess of $NF_3$ increases the concentration of free fluorine radicals, which can lead to unwanted, unselective chemical etching of exposed silicon or silicon-germanium surfaces [A1], [A2]. In $NF_3/O_2$ chemistries, the $O_2/NF_3$ ratio governs the generation of $NO$ molecules; increasing this ratio to a optimal threshold enhances $Si_3N_4$ removal rates before dilution effects eventually dominate and decrease the overall etch rate [P1].

Wafer Temperature and Sublimation Control

Wafer stage temperature is the primary physical dial used to transition between the reaction phase and the sublimation phase [T2]. During the chemical reaction step, maintaining a lower wafer stage temperature is essential to facilitate the condensation of active ammonium species and stabilize the formation of the solid $(\text{NH}_4)_2\text{SiF}_6$ salt layer [P2]. If the stage temperature is too high during this step, the reactants will desorb before reacting, suppressing the etch rate [P3]. During the subsequent sublimation step, ramping the temperature to an elevated thermal threshold is mandatory to ensure complete volatilization of the salt [A1].

Chamber Pressure and Plenum Volume

Process chamber pressure governs the mean free path of the active species [T2]. Operating at higher pressures promotes intermolecular collisions, which can increase the recombination rate of active fluorine radicals into inert molecular species [P2]. This recombination can directionally lower the etch rate but may improve selectivity by suppressing aggressive radical attack [P4]. Conversely, lower pressures increase the lifetime of radicals, aiding diffusion (Engineering Practice). The inclusion of a physical plenum (an expansion chamber) between the remote source and the wafer stage allows the radical flux to laterally diffuse and homogenize, leading to highly uniform etch profiles across large-diameter wafers [P3].

Challenges & Failure Modes

While remote plasma oxide etching provides exceptional selectivity and low physical damage, it is subject to several complex chemical and physical failure modes [P1].

Volumetric Expansion Stress

During the initial phase of the siconi process, the conversion of solid $SiO_2$ into the solid $(\text{NH}_4)_2\text{SiF}_6$ salt involves a significant volumetric expansion (Engineering Practice). In dense, multi-layered structures, such as those found in fin field effect transistor designs, this expansion can exert intense mechanical stress on adjacent delicate features (Engineering Practice). This localized stress can cause structural deformation, pattern bending, or the physical collapse of high-aspect-ratio silicon fins [P2].

Solid Salt Residues and Incomplete Sublimation

If the thermal sublimation step is non-uniform or does not reach the required activation temperature, residual ammonium hexafluorosilicate salt may remain on the wafer surface [A1]. These non-volatile solid residues act as particles, blocking subsequent epitaxial growth, metal contact deposition, or atomic layer deposition processes [A1]. This failure mode leads to high contact resistance and localized killer defects in the integrated circuit [A1].

Ion Leakage and Charging Damage

Although the remote plasma source is designed to supply only neutral species, electrostatic leakage can occur [P3]. If the grid electrode degradation occurs or if the pressure-power regime is incorrectly balanced, a weak ion-ion plasma can leak into the downstream chamber [P3]. Even low-energy ion bombardment can compromise the isotropic nature of the etch and induce wafer charging damage [T2]. Under these conditions, the accumulation of electrostatic charge on conductive features can trigger gate oxide breakdown via the antenna effect [T2].

Corner Rounding and Loss of Spacer Profiles

In applications like spacer etching, precise control over the profile is critical to prevent critical dimension (CD) loss [P4]. If hydrogen-based modification or remote plasma etching is applied to low-k spacer materials, such as SiCO, isotropic radical attack can lead to lateral trimming, spacer recess, or complete spacer loss [P4]. This degradation of the spacer profile increases parasitic capacitances and alters the effective channel length of the transistor [P4].

Technology Node Evolution

The 28nm Planar Era

At the 28nm Planar Flow node, remote plasma oxide etch was primarily introduced to replace wet hydrofluoric (HF) acid cleans in critical modules, such as pre-contact clean and pre-gate oxide deposition modules [A1]. Wet chemical cleaning faced scaling limits due to surface tension, which prevented liquid solutions from cleanly entering high-aspect-ratio contact holes (Engineering Practice). The siconi process successfully bypassed these limits, removing native oxides from the bottoms of contact vias without undercutting the surrounding dielectric materials [A1].

Transition to 14nm FinFETs

As the industry transitioned to the 14nm FinFET node, the physical architecture became fully three-dimensional [P4]. Direct RIE etching of native oxides on the vertical sidewalls of the delicate silicon fins was impossible without causing severe ion bombardment damage and fin erosion [T2], [P4]. Remote plasma oxide etching became mandatory to prepare the fin surfaces before the deposition of the high-k metal gate stacks, ensuring interface stability without degrading the fin geometry [A1]. Furthermore, hydrogen-based modification combined with downstream dry chemical etching emerged to enable damage-free spacer integration of carbon-doped low-k dielectric spacers [P4].

Scaling to 7nm and Beyond

At the 7nm FinFET node and down to contemporary gate-all-around (GAA) nanosheet structures, the margins for material loss became practically atomic [A2]. In GAA architectures, silicon nanosheets are interleaved with sacrificial silicon-germanium ($SiGe$) layers [A2]. Selectively releasing these nanosheets requires dry chemical etching processes with extreme selectivity [A2]. Engineers utilize highly specialized remote plasma chemistries with molecular-level passivation schemes to protect the $SiGe$ or Si layers dynamically during the etch [A2]. The complete avoidance of physical sputtering in remote plasma systems is what makes these sub-10nm architectures physically manufacturable [P3], [A2].

Related Processes

Remote plasma oxide etching does not operate in isolation; it is deeply integrated with several key adjacent steps in the CMOS process flow:

• Ion Implantation: In advanced spacer and contact modules, ion implantation is often used to selectively modify the top layer of a dielectric or low-k film (e [T2].g., SiCO), making it highly susceptible to downstream remote plasma or wet HF removal while the unmodified bulk material remains highly resistant [P4].
• Surface Preparation for Epitaxy: Prior to the selective epitaxial growth of source and drain junctions (such as boron-doped SiGe for p-MOS transistors), a siconi remote plasma etch is executed [A1]. This step removes any native oxide layer from the exposed silicon seed area, guaranteeing a defect-free, single-crystal epitaxial interface [A1].
• High-k Metal Gate (HKMG) Integration: Before depositing the ultra-thin interfacial oxide and high-k dielectric layer (e [A1].g., hafnium dioxide), the silicon channel surface must be atomically clean [A1]. Remote plasma chemical etching provides the necessary damage-free surface prep, directly minimizing interfacial trap density and preventing device threshold voltage shift [A1].

Future Outlook

As the semiconductor industry marches toward sub-2nm nodes, the role of remote plasma technology is expanding into the domain of atomic layer etching (ALE) [T2]. Quasi-atomic layer etching processes are being developed by separating the radical adsorption step and the desorption step into distinct, highly controlled cycles, ensuring true atomic-scale fidelity [T2].

Research is also focusing on the synthesis of novel chemical precursors to replace $NF_3$ (Engineering Practice). Alternative gases with lower global warming potential and more complex radical structures are being evaluated to tune the vibrational states of the reactive species [P2], [P3]. This tuning will allow engineers to achieve even higher selectivity ratios, enabling the continuous physical scaling of next-generation high-density 3D integrated circuits and advanced packaging architectures [T2].