Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
Understanding the Active Poly Layer in Semiconductor Integration: Physics, Deposition, and Node Evolution
In the history of microelectronics fabrication, the gate electrode of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has undergone dramatic material and structural…
Anti-Reflective Coating in Semiconductor Patterning: Optical Principles, Materials, and Process Integration
In modern semiconductor manufacturing, printing sub-wavelength features with high precision requires strict control over light propagation within the photoresist stack.
Fundamentals of Critical Dimension Trim: Physics, Mechanisms, and Advanced Node Integration
In modern semiconductor manufacturing, the relentless drive toward smaller, faster, and more power-efficient integrated circuits is governed by the scaling of physical features.
Mastering Decoupled Plasma Nitridation: Physical Principles, Process Engineering, and Advanced Node Integration
As semiconductor devices scaled below sub-micron nodes, conventional silicon dioxide ($SiO_2$) gate dielectrics faced fundamental physical limits, particularly the surge in…
Fundamental Principles of Electron Beam Technology in Advanced Semiconductor Manufacturing
In the pursuit of relentless device scaling, the semiconductor industry has continually pushed the boundaries of lithographic resolution, film deposition precision, and defect…
Fundamental Principles of Epitaxial Growth: Physical Mechanisms, Process Kinetics, and Advanced Node Integration
Epitaxial growth, derived from Greek roots meaning "to arrange upon," is a specialized deposition process where a crystalline thin film is grown on a single-crystal substrate…
Fundamental Principles of Fin Cut Trench (FCT) Technology in Advanced FinFET Integration
In the continuous pursuit of Moore's law, the semiconductor industry transitioned from planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to three-dimensional…
FOUP: Wafer Carrier and Microenvironment
A FOUP encloses wafers between compatible process tools and can reduce exposure; door opening, materials, and storage conditions still shape contamination risk.
Hard Mask: How Pattern Transfer Works
A hard mask carries a resist pattern into a later etch when resist alone would erode or distort. Follow a real SiO-mask sequence from deposition to removal.
Fundamentals of Mandrel Spacer Patterning: Principles, Integration, and Advanced Node Scaling
Mandrel-spacer patterning uses a sacrificial core and sidewalls for denser patterns. A public 7nm overview locates self-aligned pitch division in a wider flow.
Engineering the Narrow Gate Region: Physics, Process Integration, and Advanced Node Scaling
In complementary metal-oxide-semiconductor (CMOS) device scaling, shrinking gate dimensions is essential for driving density and performance improvements.
Fundamental Principles of Nickel Platinum in Advanced Semiconductor Contact Engineering
NiPt may help stabilize a nickel-based silicide contact, depending on composition and thermal history. The linked 7nm overview does not identify an NiPt alloy.