Preamorphization Implant (PAI): Physical Principles, Process Integration, and Technology Node Evolution in Semiconductor Manufacturing

Introduction

Preamorphization implant (PAI) is a semiconductor process technique in which the crystalline silicon substrate is intentionally rendered amorphous by ion bombardment prior to a dopant implantation step [P4]. The purpose is to eliminate the long-range crystalline order that gives rise to ion channeling, thereby enabling the formation of ultrashallow, sharply defined dopant profiles [T1]. In modern complementary metal-oxide-semiconductor (CMOS) manufacturing, the ability to form extremely shallow and highly activated junctions is critical for controlling short-channel effects, minimizing series resistance, and achieving target drive currents [P1].

The concept of preamorphization is rooted in the physics of ion implantation damage accumulation [P2]. When energetic ions enter a single-crystal silicon substrate, a fraction of them travel along open crystallographic channels — the so-called channeling effect — producing a deep, exponential tail in the dopant concentration profile [T1]. By destroying the periodic lattice prior to the dopant implant, PAI ensures that the dopant ions encounter a random, amorphous medium with no preferred directions, resulting in a profile governed solely by nuclear and electronic stopping [P3].

Beyond profile control, PAI has evolved to serve additional functions (Engineering Practice). In advanced nodes, germanium-based PAI introduces uniaxial compressive strain into the pMOS channel, enhancing hole mobility [P1]. Dual-element PAI schemes, such as combined Ge/C implants, have been developed to engineer silicide formation pathways and suppress agglomeration [P4]. PAI is also used in FinFET source/drain regions to facilitate selective epitaxial regrowth and contact formation [A1].

This article provides a comprehensive overview of the physical mechanisms, process principles, challenges, and evolution of PAI across technology nodes, with emphasis on the causal chains that connect implant parameters to device-level outcomes [P1].

Physics & Mechanism

Ion Channeling and the Need for Amorphization

In a single-crystal silicon lattice, atoms are arranged in a periodic structure with open channels along low-index crystallographic directions such as ⟨100⟩, ⟨110⟩, and ⟨111⟩ [T2]. When an energetic ion enters the crystal aligned with one of these channels, it experiences a reduced nuclear stopping cross-section because the channel walls of lattice atoms steer it via a series of gentle Coulombic deflections rather than hard nuclear collisions [T1]. The ion can travel significantly deeper than its projected range in a random medium, producing a characteristic channeling tail in the depth profile (Engineering Practice).

This channeling tail is problematic for ultrashallow junction formation because it deepens the metallurgical junction and degrades the profile abruptness — both of which worsen short-channel behavior [P3]. Conventional approaches such as tilting the wafer during implantation only partially mitigate channeling because some ions still find secondary channels [P3]. The most effective solution is to eliminate the crystallographic information entirely by creating an amorphous surface layer [T1].

Amorphization Physics

Amorphization occurs when the local displacement damage density exceeds a critical threshold, beyond which the lattice cannot recover its crystalline order during the implant itself [P2]. Each incident ion generates a collision cascade — a localized region of Frenkel pairs (vacancy–interstitial pairs) — and the overlapping of many such cascades eventually accumulates enough damage to destroy long-range order [T1]. The damage accumulation rate depends on the ion mass, energy, dose, and substrate temperature [P2]. Heavier ions (e.g., Ge, Xe) produce denser cascades per ion and thus amorphize at lower doses than lighter ions (e [P4].g., Si) [P2]. Lower substrate temperatures also favor amorphization because a larger fraction of the generated Frenkel pairs survives recombination within the cascade [T1].

A key structural feature of the amorphized layer is the amorphous/crystalline (a/c) interface [P4]. Below this interface, the substrate remains crystalline, but the region just beneath the original a/c interface — known as the end-of-range (EOR) damage zone — contains a high density of residual interstitial defects [P2]. These defects form because the implant damage gradient is steep near the a/c interface, and some displaced atoms are pushed just beyond it into the crystalline region [T1][P2].

Solid-Phase Epitaxial Regrowth (SPER)

After PAI and the subsequent dopant implant, the wafer undergoes thermal annealing to regrow the amorphous layer and electrically activate the dopants [P2]. During solid-phase epitaxial regrowth (SPER), the crystalline silicon below the a/c interface serves as a template, and the amorphous silicon recrystallizes layer by layer toward the surface [P3]. SPER is a thermally activated process — its rate increases exponentially with temperature — and it can be completed at temperatures lower than those required for conventional furnace annealing of crystalline damage [P3].

A critical advantage of SPER for junction formation is that dopant atoms incorporated in the amorphous layer tend to occupy substitutional lattice sites during regrowth, achieving near-complete electrical activation without requiring the high temperatures that would cause significant dopant diffusion [P3]. This is why PAI combined with rapid thermal annealing (RTA) became a standard approach for forming ultrashallow, highly activated junctions — the amorphous layer ensures no channeling tail, and SPER ensures high activation at a low thermal budget [P3].

Strain Engineering via PAI

In advanced CMOS, particularly for pMOS devices, Ge PAI serves a dual purpose [P1]. Beyond suppressing channeling, the larger atomic radius of Ge (relative to Si) means that Ge atoms incorporated during SPER expand the local lattice parameter [P4]. When Ge PAI is applied to source/drain extension regions, the resulting lattice expansion generates a compressive strain component that is transferred into the channel, lifting valence band degeneracy and reducing the hole effective mass [P1]. This uniaxial compressive strain is especially effective because it maintains mobility enhancement under high vertical electric fields — a regime where biaxial strain techniques lose effectiveness [P1].

Impurity Interactions in PAI Systems

The choice of PAI species also affects dopant and defect behavior during annealing [P2]. In systems using BF₂ implants into Xe-preamorphized silicon, the Xe atoms trapped at EOR defects interact with fluorine from the BF₂ molecule [P2]. During annealing, F becomes mobile and can either segregate toward the surface or migrate inward to co-enrich with Xe near the B/F range end, forming stable trapping complexes that suppress further dopant diffusion [P2]. This coupling between the PAI species and the dopant species illustrates that PAI is not merely a "damage source" but an active participant in the defect chemistry of junction formation [P2].

Process Principles

PAI Species Selection

The choice of PAI ion species is the most fundamental process decision because it determines the damage density per ion, the a/c interface sharpness, the strain contribution, and the chemical interactions with subsequent dopants (Engineering Practice).

• Silicon (Si⁺): The lightest commonly used PAI species (Engineering Practice). Si self-implantation produces no foreign impurity, making it the cleanest option, but it requires higher doses to achieve full amorphization and produces a relatively gradual a/c interface [P3].
• Germanium (Ge⁺): The most widely used PAI species for advanced CMOS [P1]. Ge is heavier than Si, so it amorphizes at lower doses with a sharper a/c interface [P4]. Ge also contributes to strain engineering in pMOS devices, providing compressive channel strain [P1]. Ge PAI suppresses boron channeling and improves boron activation efficiency, leading to shallower junctions and higher surface concentrations [P1].
• Xenon (Xe⁺): An inert gas ion that is even heavier than Ge (Engineering Practice). Xe PAI produces the sharpest a/c interfaces and enables precise spatial separation of EOR defects from the junction [P2]. However, Xe does not contribute to strain engineering and can introduce stable gas-filled voids [P1].
• Carbon (C⁺): Used as a co-implant or secondary PAI species (Engineering Practice). C acts as a strong amorphizing agent and an interstitial trap, suppressing transient-enhanced diffusion (TED) of boron [P3]. In dual Ge/C PAI schemes, C modulates silicide nucleation pathways by stabilizing amorphous interlayers [P4].

Implant Energy

PAI implant energy determines the depth of the amorphous layer and the position of the a/c interface relative to the subsequent junction [P2]. Increasing the PAI energy shifts the damage peak deeper, producing a thicker amorphous layer and a deeper EOR defect band [P2]. The amorphous layer must be thick enough to completely contain the dopant implant profile — otherwise, channeling tails will still form below the a/c interface [P3]. However, making the amorphous layer excessively deep pushes EOR defects closer to the metallurgical junction, increasing leakage risk [P2]. The process window therefore requires balancing channeling suppression against EOR defect proximity [T1].

In the context of silicide formation, the PAI depth must also be shallow enough that the amorphous layer is fully consumed during the silicidation reaction; otherwise, residual amorphous silicon would remain as a high-resistivity defect [P4].

Implant Dose

The PAI dose must exceed the amorphization threshold to ensure a continuous amorphous layer from the surface to the a/c interface [P4]. Below threshold, a buried amorphous layer may form first, and a considerably higher dose is needed before a continuous surface-to-depth amorphous layer is achieved [T1]. Increasing the dose beyond the threshold increases the damage density and the width of the EOR defect band, which can enhance strain effects (in the case of Ge) but also increases the risk of residual defects after annealing [P1].

Substrate Temperature

Lower substrate temperatures during PAI favor amorphization because more Frenkel pairs survive recombination within each cascade [T1]. Cryogenic implantation can achieve full amorphization at lower doses, reducing the overall damage budget [P3]. However, cryogenic implants present engineering challenges in dose uniformity and wafer handling [P1].

Annealing Conditions

The annealing strategy following PAI must accomplish two goals: complete SPER of the amorphous layer and activate the dopants, all while minimizing diffusion [P2]. Rapid thermal annealing (RTA) with high ramp rates and short dwell times is preferred because it completes SPER quickly and limits the time available for dopant diffusion [P3]. The temperature must be high enough to fully regrow the amorphous layer — incomplete regrowth leaves residual amorphous regions that are electrically inactive and structurally defective [T1].

The interaction between annealing temperature and the residual interstitial population is governed by the "+1" model: after initial Frenkel pair recombination, the dominant residual damage is approximately one interstitial per implanted ion (the implanted atom itself, once it occupies a lattice site) [T1]. These excess interstitials drive TED of dopants like boron, making the annealing thermal budget a critical parameter [P3].

Challenges & Failure Modes

End-of-Range Defects and Junction Leakage

The most persistent challenge of PAI is the EOR defect band (Engineering Practice). During SPER, the amorphous layer regrows cleanly from the crystalline template, but the interstitial-rich region just below the original a/c interface does not benefit from this template-driven regrowth [P2]. These excess interstitials coalesce into extended defects — typically {311} defects and dislocation loops — during high-temperature annealing [T1]. If the EOR defect band overlaps with the depletion region of the junction, these defects act as generation-recombination centers, causing elevated junction leakage [T1].

The physical mechanism is that dislocation loops and {311} defects introduce mid-gap energy states that facilitate thermal generation of carriers in the depletion region [T1]. The leakage current increases with defect density and with the overlap between the defect band and the depletion region [T1]. This is why PAI energy must be carefully tuned to place the EOR defects below the metallurgical junction [P2].

Transient-Enhanced Diffusion (TED)

Excess interstitials from the implant damage cause TED — a transient, non-equilibrium burst of dopant diffusion that occurs during the early stages of annealing [T1]. TED is particularly severe for boron because boron diffuses via an interstitial-mediated mechanism [P3]. The excess interstitials from PAI and the dopant implant interact with boron to form mobile boron-interstitial pairs, dramatically accelerating boron diffusion beyond the equilibrium value [T1].

TED deepens the junction and reduces the peak concentration, both of which degrade device performance [T1]. PAI can either mitigate or worsen TED depending on the integration: if the amorphous layer fully contains the dopant, SPER removes much of the damage during regrowth, and the "+1" interstitial population is relatively well-controlled [P2]. However, if the PAI damage extends beyond the dopant profile, the excess interstitials in the EOR zone can still drive TED [T1].

Residual Amorphous Regions

If the annealing temperature or duration is insufficient to complete SPER, residual amorphous silicon remains [P2]. Amorphous silicon has extremely high resistivity because the lack of long-range order means that dopant atoms cannot occupy well-defined substitutional sites — they are electrically inactive [T1]. In a device, residual amorphous regions in the source/drain create a high series resistance path that degrades drive current [A2].

Reverse Annealing

For implants below the amorphization threshold, a "reverse annealing" phenomenon can occur between approximately 450°C and 550°C [P2]. In this regime, interstitial damage competes with boron for substitutional sites or forms inactive boron-interstitial complexes, causing the carrier concentration to drop abruptly before recovering at higher temperatures [T1]. PAI avoids this regime by ensuring the dose is above the amorphization threshold, so SPER rather than point-defect annealing governs activation [T3].

Strain–Leakage Trade-off in Ge PAI

For Ge PAI in pMOS, increasing the Ge dose enhances compressive channel strain and improves hole mobility, but it also deepens the EOR defect band and increases junction leakage [P1]. This trade-off requires careful optimization of the Ge dose and energy to balance the strain benefit against the leakage penalty [P1]. The need to balance strain effects and ultrashallow junction leakage is a central engineering challenge in Ge PAI optimization [P1].

Silicide Formation Perturbations

In advanced nodes where PAI is applied before source drain recess and silicidation, the amorphous layer can alter the silicide phase formation sequence [P4]. High-dose C PAI, for instance, suppresses the nucleation of conventional Ni-rich phases and instead promotes the formation of an amorphous Ni₁₋ₓPtₓSi interlayer that only crystallizes at higher temperatures [P4]. While this can improve agglomeration resistance, it also narrows the process window for achieving the desired low-resistivity phase [P1].

Technology Node Evolution

28nm and Above: Planar CMOS with Ge PAI for pMOS

At the 28nm node and above, planar CMOS devices used Ge PAI primarily for boron channeling suppression and activation improvement in pMOS source/drain extensions [P1]. The 28nm planar flow represents a generation where PAI was integrated as a standard step in the extension implant sequence [P2]. Ge PAI at this node demonstrated up to 32% improvement in effective hole mobility at moderate electric fields, and optimization of dose and energy extended this to 43% for shorter gate lengths [P1].

The strain engineering benefit of Ge PAI was also recognized at this node [P1]. The comprehensive compressive strain of up to 3.0% introduced by Ge PAI in the channel was confirmed by advanced diffraction techniques, demonstrating that PAI could serve as a low-cost, manufacturable strain-enhancement technique alongside more complex approaches [P1].

14nm: FinFET Transition and Contact Engineering

The transition to FinFET architecture at 14nm fundamentally changed the role of PAI [A2]. In planar devices, PAI was applied to the 2D source/drain surface (Engineering Practice). In FinFETs, the 3D fin geometry and the need for selective epitaxial source/drain regrowth required PAI to be applied within etched recesses in the fin [A1]. The 14nm FinFET flow illustrates this integration [A2].

At this node, PAI was used to amorphize the source/drain regions before epitaxial growth, serving two functions: (1) improving the crystalline quality of the regrown epitaxial layer by providing a clean regrowth interface, and (2) enabling strain transfer from the epitaxial SiGe (for pMOS) or Si:C (for nMOS) into the channel [A1]. The PAI step was also used in contact formation sequences, where amorphization of the source/drain surface improved contact morphology and reduced contact resistance [A2].

The concave source/drain structures described in FinFET contact patents used PAI to create amorphous regions in the source/drain trenches, which were subsequently regrown during contact annealing [A1]. The amorphous regions, referred to as PAI regions in the patent literature, were formed by implanting Ge or Si into the substrate at controlled energies to convert the crystal structure to an amorphous state [A1].

7nm and Beyond: Multi-Species PAI and Co-Optimization

At 7nm and beyond, the 7nm FinFET flow represents a generation where PAI faces extreme constraints [A2]. Junction depths are measured in single-digit nanometers, and the EOR defect band must be placed within a few nanometers of the surface — a nearly impossible target with conventional single-species PAI [P2]. Multi-species PAI schemes, such as dual Ge/C implants, were developed to combine the strain benefits of Ge with the interstitial-trapping capability of C [P4].

The evolution from single-species to dual-species PAI reflects a broader trend: as nodes shrink, PAI must be co-optimized with doping strategy, dopant activation thermal budget, and silicide formation [T1]. At advanced nodes, PAI can no longer be treated as an isolated step; its effects on EOR defect placement, TED, strain, and silicide nucleation must all be simultaneously managed [P4][P1].

Related Processes

PAI does not operate in isolation (Engineering Practice). It is tightly coupled with several adjacent process steps:

Dopant Implantation: PAI is always followed by a dopant implant — typically boron or BF₂ for p-type junctions, or phosphorus/arsenic for n-type [P3]. The PAI amorphous layer defines the stopping medium for the dopant, and the a/c interface depth relative to the dopant range determines the residual channeling and EOR defect proximity [P3]. In advanced flows, pocket implant (halo) steps may also interact with PAI damage, requiring careful sequencing [P2].

Rapid Thermal Annealing / Spike Anneal: The annealing step following PAI governs SPER completion, dopant activation, and TED [P3]. The thermal budget must be sufficient to fully regrow the amorphous layer while minimizing diffusion [P3]. Millisecond annealing (laser or flash lamp) has been explored to further decouple activation from diffusion [P2].

Silicidation: PAI directly influences silicide phase formation [P4]. The amorphous silicon reacts differently with metals (Ni, Co, Ti) than crystalline silicon, altering nucleation temperatures and phase sequences [P4]. Dual Ge/C PAI can suppress unwanted Ni-rich phases and stabilize the desired monosilicide phase [P4].

Selective Epitaxial Growth (SEG): In FinFET source/drain formation, PAI of the recessed fin surface can improve epitaxial nucleation and quality [A2]. The amorphous layer provides a damage-free regrowth surface when properly annealed, and the Ge content from PAI can contribute to the lattice matching for SiGe epitaxy [A1].

Stress Memorization Technique (SMT): PAI-induced damage can interact with subsequent stress memorization processes, where amorphization and recrystallization "freeze in" stress from overlying films [P1]. The pattern memorization and stress engineering literature describes related concepts [P1].

Future Outlook

The future of PAI is shaped by several converging trends in advanced semiconductor manufacturing:

Cryogenic Implantation: As junction depths approach the atomic scale, cryogenic PAI offers the ability to achieve full amorphization at lower doses, reducing the EOR defect burden [P3]. Cryogenic implants also produce sharper a/c interfaces due to reduced dynamic annealing during the cascade, which improves the spatial control of the amorphous layer [T1].

Co-Implantation Optimization: Multi-species PAI schemes (e (Engineering Practice).g., Ge + C, Ge + F) will continue to evolve, with each species serving a specific function — strain, interstitial trapping, or defect passivation (Engineering Practice). The interaction between PAI species and dopant species, as demonstrated by the Xe–F coupling in BF₂ systems [P2], suggests that PAI chemistry can be engineered to actively suppress TED and stabilize junctions.

Advanced Annealing Integration: The combination of PAI with advanced annealing techniques — including non-melt laser annealing, flash annealing, and microwave annealing — will be critical for achieving the simultaneous goals of complete SPER, full activation, and minimal diffusion [P2]. These techniques offer spatially and temporally controlled thermal profiles that can be optimized for specific PAI conditions [P3].

Gate-All-Around (GAA) Architectures: As the industry transitions from FinFET to GAA nanosheet devices, the 3D geometry of source/drain regions becomes even more complex [A2]. PAI will need to be adapted for nanosheet structures, where the amorphization must be controlled across multiple suspended silicon channels [P4]. The integration of PAI with threshold voltage implant and channel implant steps in GAA flows will require new levels of co-optimization [P3].

Machine Learning–Assisted Process Optimization: The multi-parameter nature of PAI (species, energy, dose, temperature, annealing) makes it an ideal candidate for ML-assisted optimization (Engineering Practice). By training models on physical simulations and experimental data, process engineers can identify optimal PAI conditions that simultaneously satisfy junction depth, leakage, activation, and strain targets [P3].

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References

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