Thermal Oxidation in Semiconductor Manufacturing: Physical Principles, Mechanisms, and Process Integration

Introduction

Thermal oxidation is one of the most foundational unit processes in semiconductor manufacturing, involving the controlled reaction of a silicon substrate with an oxidizing ambient—typically molecular oxygen (O₂) or water vapor (H₂O)—to form silicon dioxide (SiO₂) at elevated temperatures [P1]. The process is unique among thin-film fabrication techniques because the oxide is grown from the substrate itself, producing an exceptionally clean, high-quality dielectric with a near-perfect interface to the underlying silicon [T1]. This self-forming interface is the primary reason oxidation became indispensable in integrated circuit manufacturing [T1].

The importance of oxidation spans multiple roles: gate dielectric formation, isolation trench filling, sacrificial oxide growth for surface cleaning, and screen oxides used during ion implantation [T1]. The SiO₂/Si interface exhibits among the lowest interface trap densities of any dielectric/semiconductor system, which directly underpins the electrical performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) [T2]. Beyond its electrical quality, thermally grown SiO₂ serves as an excellent masking layer against dopant diffusion, enabling selective doping through patterned oxide windows [T1].

From a device physics perspective, the quality of the gate oxide directly sets the threshold voltage stability, channel mobility, and leakage characteristics of transistors [T2]. Even as the industry has transitioned to deposited high-k dielectrics at advanced nodes, thermal oxidation remains critical for forming interfacial SiO₂ layers, sacrificial oxides, and shallow trench isolation liners [T1]. Understanding the physical and chemical mechanisms that govern oxidation kinetics is therefore essential for any semiconductor process engineer or student seeking to master device fabrication [T1]. For a deeper dive into one specific application, see our article on gate oxidation [T1].

Physics & Mechanism

The Deal–Grove Framework

The cornerstone of oxidation theory is the Deal–Grove model, proposed in 1965, which describes silicon thermal oxidation as a series of three sequential transport and reaction steps: (1) transport of the oxidant from the gas phase to the oxide surface, (2) diffusion of the oxidant through the existing oxide layer, and (3) chemical reaction at the Si/SiO₂ interface to form new oxide [P1]. The model assumes steady-state flux continuity, meaning the flux of oxidant arriving at the surface equals the flux diffusing through the oxide and the flux consumed at the interface [P1].

The gas-phase transport is described by a linearized approximation analogous to Newton's law of cooling, where the flux F₁ is proportional to the difference between the equilibrium oxidant concentration in the oxide (C*) and the actual surface concentration (C₀) [P1]. The equilibrium concentration follows Henry's law: C* = Kp, where K is Henry's constant and p is the partial pressure of the oxidant [P1]. The diffusion through the oxide follows Fick's law, F₂ = D_eff(dC/dx), where D_eff is the effective diffusion coefficient [P1]. Under steady-state assumptions, the concentration gradient within the oxide is linear, and the interfacial reaction rate is proportional to the oxidant concentration at the interface [P1].

The resulting unified kinetic equation is:

x₀² + A·x₀ = B(t + τ)

where x₀ is the oxide thickness, t is the oxidation time, A is a parameter related to the linear rate constant, B is the parabolic rate constant, and τ is an effective initial time correction term [P1]. This equation elegantly captures the two limiting regimes: for thin oxides, the interfacial reaction is rate-limiting and growth is approximately linear (x₀ ∝ t); for thicker oxides, diffusion through the growing oxide becomes the bottleneck and growth follows a parabolic law (x₀ ∝ √t) [P1].

Chemical Reaction Principles

In dry oxidation, the overall chemical reaction is:

Si + O₂ → SiO₂

In wet oxidation, the reaction is:

Si + 2H₂O → SiO₂ + 2H₂

The oxidizing species are molecular O₂ and H₂O, respectively, consistent with Henry's law assumptions [P1]. The reaction occurs at the Si/SiO₂ interface, meaning that as oxide grows, silicon is consumed [P1]. The volume expansion accompanying this reaction is significant: a unit volume of silicon converts to approximately 2.2 times that volume of SiO₂ [P2]. Because the substrate constrains lateral expansion, the oxide grows upward, with roughly 46% of the final oxide thickness below the original silicon surface and 54% above it [T2].

The Interfacial Silicon Emission Model

While the Deal–Grove model provides an excellent macroscopic framework, it has known limitations in describing the initial rapid oxidation of ultrathin oxides and differences between wet and dry oxidation [P2]. The interfacial silicon atom emission model addresses these gaps by recognizing that the oxidation reaction at the Si/SiO₂ interface is accompanied by the emission of silicon interstitial atoms into the oxide and into the substrate [P2]. These Si interstitials can inhibit the formation of new reactive sites at the interface, thereby creating a feedback mechanism that modulates the interfacial reaction rate [P2].

In dry oxidation, the rate of silicon emission is substantial, leading to a high concentration of Si interstitials near the interface that suppress the interfacial reaction rate constant over time [P2]. This suppression is the mechanism behind the initial oxidation enhancement observed in dry O₂ ambients—the reaction rate constant k decreases as oxidation proceeds and the interstitial concentration builds up [P2]. In wet oxidation, the silicon emission rate is significantly lower—approximately one-fifth that of dry oxidation—so the interfacial Si interstitial concentration remains lower, the self-inhibition effect is weaker, and wet oxidation exhibits negligible initial oxidation enhancement and a linear pressure dependence of oxidation rate [P2].

This model also provides a unifying explanation for oxidation-enhanced diffusion (OED) and oxidation stacking faults (OSF), both of which are caused by the injection of excess silicon interstitials into the substrate during oxidation [P2]. The ratio of Si emission between wet and dry oxidation is consistent with the observed differences in OSF sizes between the two ambients [P2].

Volume Expansion and Stress Effects

The 2.2× volume expansion during silicon oxidation has profound consequences for device integration [T2]. On planar surfaces, the expansion is accommodated primarily by upward growth (Engineering Practice). However, on shaped or patterned surfaces—such as in local oxidation of silicon (LOCOS) structures—the expansion is constrained laterally, generating compressive stress in the oxide and tensile stress in the surrounding silicon [T2]. This stress affects oxidation kinetics in two ways: it can slow the oxidant diffusion through the stressed oxide, and it can modify the interfacial reaction rate [P1]. The viscoelastic properties of SiO₂ play a role here, with a transition temperature around 950–1000°C where stress relaxation behavior changes, producing an observable break point in the activation energy of the parabolic rate constant [P2].

Process Principles

Temperature Effects

Temperature is the most influential parameter in thermal oxidation, affecting all three kinetic steps—gas-phase transport, diffusion, and interfacial reaction—through Arrhenius-type relationships [P3]. Increasing temperature raises the equilibrium solubility of the oxidant in SiO₂, increases the diffusion coefficient of the oxidant through the oxide, and accelerates the interfacial chemical reaction [P1]. The net effect is that higher temperature increases both the linear and parabolic rate constants, shortening the time required to achieve a target oxide thickness [P1].

The direction of the temperature effect is unambiguous: higher temperature → faster oxidation in both linear and parabolic regimes [P3]. However, there are subtleties (Engineering Practice). The activation energy of the interfacial reaction differs from that of diffusion, so the relative importance of the two rate-limiting mechanisms shifts with temperature [P2]. Additionally, viscoelastic transitions in SiO₂ introduce non-Arrhenius behavior around 950–1000°C, where the stress state of the oxide changes and the effective oxidation rate deviates from simple thermal activation [P2].

Oxidant Ambient: Dry vs [P2]. Wet

The choice of oxidant ambient fundamentally changes both the rate and the quality of the resulting oxide [P2]. Water vapor has a solubility in SiO₂ approximately three orders of magnitude greater than that of O₂, and it diffuses through the oxide more rapidly [P2]. Consequently, wet oxidation proceeds at a significantly faster rate than dry oxidation, making it preferred for growing thick oxides such as field oxides or isolation oxides [T1]. Dry oxidation, being slower, produces denser, higher-quality oxide with superior interface properties, making it the preferred method for thin gate oxides [T1].

The pressure dependence also differs between the two ambients (Engineering Practice). In wet oxidation, the oxidation rate is approximately linearly proportional to the water vapor partial pressure, because the interfacial Si emission rate is low and the reaction rate constant is not significantly suppressed at higher pressures [P2]. In dry oxidation, the oxidation rate scales sub-linearly with O₂ pressure (proportional to p^n where n < 1), because higher pressures lead to more Si interstitial emission, which suppresses the interfacial reaction rate [P2].

Crystallographic Orientation

The silicon surface orientation affects the density of available bonding sites at the Si/SiO₂ interface [P2]. (111)-oriented silicon has a higher surface atom density than (100)-oriented silicon, leading to a higher linear rate constant for (111) substrates [P2]. The parabolic rate constant, being controlled by diffusion through the oxide rather than interfacial reaction, is relatively insensitive to orientation [T1][P2].

Substrate Doping

Heavily doped silicon substrates oxidize faster than lightly doped ones, particularly in the linear regime [T2]. This effect arises because high doping concentrations can enhance the interfacial reaction rate through band-bending effects at the Si/SiO₂ interface [T2]. The Debye length in the oxide, which characterizes the distance over which space charge effects are significant, plays a role in the initial oxidation regime [P1]. For a detailed treatment of how doping affects semiconductor properties, see our article on thermal diffusion [T2].

Pressure

Elevated pressure oxidation (high-pressure oxidation) increases the equilibrium concentration of oxidant in the oxide (C* ∝ p by Henry's law), directly increasing the diffusion flux through the oxide and the concentration at the interface [P3]. This accelerates oxidation in both linear and parabolic regimes, allowing thicker oxides to be grown at lower temperatures or in shorter times—a valuable capability when thermal budget constraints are tight [P1].

Challenges & Failure Modes

Initial Rapid Growth and Ultrathin Oxide Control

One of the most persistent challenges in oxidation is the anomalously rapid growth observed in the initial regime for ultrathin oxides—typically below approximately 20–30 nm [P3]. The Deal–Grove model underestimates growth in this regime, and the interfacial silicon emission model partially explains this through the time-dependent suppression of the reaction rate constant [P2]. However, additional factors such as space charge effects, surface preparation conditions, and the Debye length in the oxide also contribute [P1]. For ultrathin gate oxides, this non-ideal behavior makes precise thickness control extremely difficult and has motivated the industry's transition to deposited dielectrics for sub-2nm gate oxides [T1]. For more on this evolution, see our article on gate oxidation [T1].

Stress-Induced Defects

The 2.2× volume expansion during oxidation generates significant stress, particularly in non-planar or patterned structures [T2]. In LOCOS technology, lateral oxidation under the nitride mask creates the characteristic "bird's beak" transition region, which consumes active area and introduces stress non-uniformities [T2]. In shaped structures, the stress cannot be easily accommodated and may lead to dislocation generation in the silicon substrate, oxidation-induced stacking faults (OSF), or even oxide cracking under extreme conditions [P2].

Non-Uniform Oxide Thickness

Variations in temperature uniformity across the wafer, gas flow dynamics, and local doping concentrations can lead to within-wafer and wafer-to-wafer thickness non-uniformity [T2]. Because oxide thickness directly impacts device parameters such as threshold voltage and gate capacitance, even small variations can cause significant device parameter spread [T1]. The problem is exacerbated at the wafer edge, where gas flow patterns and temperature profiles are less controlled (Engineering Practice).

Interface Quality and Contamination

The quality of the Si/SiO₂ interface is paramount for device performance [T2]. Metallic contamination, organic residues, or particles on the silicon surface before oxidation can become incorporated into the oxide or trapped at the interface, creating charge traps and leakage paths [P2]. Even trace levels of metallic contaminants (such as Fe, Cu, or Na) can severely degrade oxide integrity and cause device reliability failures such as time-dependent dielectric breakdown (TDDB) [A2]. For a process that addresses interface states, see our article on forming gas anneal [T1].

Pattern Loading Effects

In patterned wafers, the local density of exposed silicon affects oxidation rates through two mechanisms: consumption of oxidant in densely packed regions and stress interactions between adjacent features [P2]. Regions with high silicon exposure area consume more oxidant locally, potentially depleting the ambient and reducing the local oxidation rate—a phenomenon known as pattern loading [P2]. This is particularly problematic in advanced nodes where feature dimensions approach the scale at which lateral oxidant diffusion becomes relevant [T2].

Technology Node Evolution

28nm and Above: Planar CMOS

At the 28nm node and above, planar CMOS transistors relied on thermally grown SiO₂ as the gate dielectric, with typical gate oxide thicknesses still within the range where Deal–Grove kinetics applied reasonably well [T1]. Wet oxidation was used for thick field oxides and isolation structures, while dry oxidation was employed for gate oxide growth [P2]. The 28nm planar flow represents this era well, where LOCOS or shallow trench isolation (STI) oxides were grown thermally [A2]. The thermal budget was still relatively generous, and furnace-based batch oxidation was the standard approach [T1].

14nm: FinFET Transition

The transition to FinFET architectures at the 14nm node (14nm FinFET flow) fundamentally changed oxidation requirements [T1]. The three-dimensional fin structures introduced non-planar surfaces where stress and volume expansion effects became much more complex (Engineering Practice). Oxidation on fin sidewalls—which are (110)-oriented on (100)-oriented substrates—introduced orientation-dependent kinetics that had to be accounted for in process design [P3]. Additionally, the gate dielectric had transitioned to high-k materials (such as HfO₂) deposited by atomic layer deposition (ALD), but a thin interfacial SiO₂ layer was still thermally grown to preserve channel mobility [T1].

The thermal budget at 14nm became significantly more constrained due to the need to maintain shallow junctions and preserve doping profiles established by ion implantation [T1]. This drove the adoption of rapid thermal processing (RTP) and single-wafer oxidation chambers that could achieve precise temperature control with short process times [T1]. For more on this topic, see our article on rapid thermal processing [T1].

7nm and Beyond

At the 7nm node (7nm FinFET flow) and beyond, the role of thermal oxidation has shifted substantially [T1]. Gate dielectrics are now entirely deposited high-k materials, and the interfacial oxide layer is carefully engineered—often through controlled chemical oxide growth or rapid thermal oxidation rather than conventional furnace processes [T1]. The thermal budget is extremely tight, as dopant diffusion must be minimized to preserve ultra-shallow junctions [T1].

Oxidation is still critical for sacrificial oxide growth (for surface cleaning and hydrogen termination prior to epitaxy), STI liner oxidation, and gate spacer formation [T1]. However, the process windows have narrowed dramatically, and the interactions between oxidation and adjacent process steps—such as source drain recess and epitaxial growth—must be carefully co-optimized [T1].

At the most advanced nodes, including gate-all-around (GAA) architectures, the challenges extend to oxidation of nanosheet or nanowire channels, where the non-planar geometry and extreme dimensions push the limits of Deal–Grove applicability [T1]. Stress effects, orientation-dependent kinetics, and the need for conformal oxidation on all surfaces of the channel simultaneously represent frontier challenges for oxidation process engineering [P3].

Related Processes

Thermal oxidation does not exist in isolation; it is deeply interconnected with numerous adjacent process steps [P3]. Sacrificial oxide growth followed by etching is a standard surface preparation technique that removes damaged silicon and contaminants before critical steps such as gate oxide formation or epitaxial deposition [T1]. The oxidation step generates a clean, high-quality Si/SiO₂ interface, and the subsequent oxide removal by hydrofluoric acid (HF) etching exposes a pristine silicon surface [P2].

Screen oxides are grown before ion implantation to prevent channeling and protect the silicon surface from contamination [T1]. These thin oxides are subsequently removed (Engineering Practice). The oxidation process also interacts with doping profiles: the injection of silicon interstitials during oxidation drives oxidation-enhanced diffusion of dopants, which must be accounted for in junction design [P2]. For a discussion of how dopant profiles are managed, see our article on thermal diffusion [T1].

Following oxidation, particularly for gate dielectrics, post-oxidation annealing—whether in nitrogen, nitrous oxide, or forming gas—is often performed to improve interface quality and reduce trap density [T1]. The forming gas anneal is especially important for passivating dangling bonds at the Si/SiO₂ interface, reducing interface trap density (D_it) and improving channel mobility [T1].

In isolation technology, the LOCOS process directly exploits the volume expansion and lateral oxidation behavior of silicon [T2]. The active area definition step relies on the quality and uniformity of the field oxide, while the transition to STI required significant innovation in oxide deposition and chemical-mechanical polishing (CMP) to replace thermal oxidation for isolation fill, though thermal liner oxides remain important [T1].

Future Outlook

The future of thermal oxidation in semiconductor manufacturing lies in several emerging directions [T1]. First, as devices transition to three-dimensional architectures such as GAA nanosheets and complementary FETs (CFETs), the need for conformal and orientation-independent oxidation on complex geometries will drive the development of new process techniques, potentially including plasma-enhanced oxidation or low-pressure oxidation with carefully controlled stress management [T1].

Second, the integration of novel channel materials—such as SiGe, germanium, and III-V compounds—requires understanding oxidation mechanisms beyond silicon [T1]. For example, the thermal oxidation of Cu films demonstrates that different materials exhibit fundamentally different oxidation phase behavior, where temperature, partial pressure, and crystallographic orientation jointly determine the final oxide phase [P3]. Similar complexity is expected for germanium and III-V oxides, where the thermodynamically stable oxides may not have the favorable interface properties of SiO₂ on silicon [P2].

Third, the role of oxidation in emerging memory technologies—such as resistive RAM (RRAM), where controlled oxide formation is central to device operation—requires atomic-level precision that pushes beyond traditional furnace or RTP capabilities [T1]. The combination of ALD with thermal oxidation, as seen in patent literature where silicon-based dielectrics deposited by ALD are subsequently thermally oxidized, represents a hybrid approach that leverages the conformality of ALD with the interface quality of thermal oxidation [A1].

Finally, machine learning and physics-informed process modeling are beginning to play a role in oxidation process development, offering the potential to optimize multi-parameter oxidation recipes while accounting for the complex interactions between temperature, pressure, ambient, orientation, doping, and stress that classical models treat only approximately [P1].

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References

• [P1] B. E. Deal and A. S. Grove, "General Relationship for the Thermal Oxidation of Silicon," J [P1]. Appl. Phys., 1965.
• [P2] K. Watanabe et al., "Simulation of wet oxidation of silicon based on the interfacial silicon emission model and comparison with dry oxidation," J [P2]. Appl. Phys., 2001.
• [P3] R. Choudhary et al., "Oxidation mechanism of thin Cu films: A gateway towards the formation of single oxide phase," AIP Advances, 2018 [P3].
• [T1] R. F. Pierret, Modern Semiconductor Devices for Integrated Circuits - Device Fabrication Technology, 2010 [T1].
• [T2] J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology, 2000 (Engineering Practice).
• [A1] US Patent Application US-2025305135-A1, "Semiconductor device with spacer layers formed by precursor compound, film deposited with the same, and method of manufacturing the film," 2024.
• [A2] US Patent US-12289913-B1, "Device with metal field plate extension," 2024.