Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
Why Replacement Metal Gate Starts with a Dummy Gate
Understand how a dummy gate preserves geometry and what must remain intact when the final metal gate replaces it.
Why STI Can Be Recessed After Filling and CMP
See why STI filling, CMP and later recess can serve different geometric goals in a device integration sequence.
Why expose a 7nm gate contact twice?
LELE divides a target pattern between two lithography-and-etch passes. Each exposure handles a less crowded subset, but overlay and edge placement matter when the subsets are combined. The CON/CB gate-contact sequence in this 7nm Flow contains E1 and E2 imaging and memorization-layer transfer, even though its step names do not spell out LELE.
Color filters, clear layers and microlenses: three different jobs in a BSI pixel
Color filters select the light reaching a pixel, a clear base prepares the surface above the filter array, and a microlens redirects light toward the sensing region. Reading these structures as three interchangeable “sensitivity layers” misses why the process needs all three.
Why conformal coverage is not complete gap fill: liner versus FCVD
Conformal deposition describes coverage along an existing surface. Gap fill asks whether material occupies the interior volume. Films can grow uniformly on both walls yet meet at the entrance before the interior is filled. FCVD uses a mobile depositing network to improve filling, while introducing its own conversion and material-stability requirements. A conformal liner remains useful because it has a different job in the same trench.
Hardmask versus etch-stop layer: pattern placement and depth control
A hardmask retains a pattern so that material is removed through selected openings. An etch-stop layer uses a difference in removal rates to protect an interface or provide margin for changing to another etch stage. Both may use silicon nitride, but a shared material does not imply a shared job. Locate the layer relative to the material being removed, then ask which boundary it must preserve.
Photodiode, transfer gate and FD: from charge to readout
A pixel voltage is the result of charge generation, collection, storage, transfer, and conversion. Calling every n-type region photosensitive confuses the photodiode with its readout node. Treating the surface p-type pinning region as extra storage volume also misses its purpose.
Self-aligned vs conventional contacts: which boundary can overlap?
A contact must reach its intended terminal while remaining insulated from the neighboring gate. Conventional placement relies strongly on the landing position and available spacing. Self-aligned integration also uses existing dielectric structures to constrain the opening. This changes the tolerance to geometric overlap; it does not make arbitrary misalignment safe.
Why bond before thinning a backside-illuminated sensor?
Backside illumination involves more than turning a device drawing upside down. Sensor silicon must be removed to a state suitable for later electrical and optical integration, while the progressively thinner structure still has to survive processing and handling. Bonding first supplies support for that removal.
28nm STI CMP Mechanism: Planarization Physics, Interfacial Chemistry, and Defect Control
Function in the Complete Flow In advanced integrated circuit manufacturing, shallow trench isolation (STI) serves as the primary structural boundary preventing parasitic leakage…
7nm Fin Recess Mechanism: Physics, Integration, and Fin Height Control
Function in the Complete Flow In sub-10nm logic manufacturing, the fin recess etch serves as the critical dimensional-setting step that transforms a planarized shallow trench…
STI CMP Effects on Pixel and Periphery Integration in 40nm BSI CIS
Function in the Complete Flow In a 40nm backside illumination (BSI) CMOS image sensor (CIS), shallow trench isolation (STI) chemical mechanical planarization (CMP) acts as the…