Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
Short-Channel Effects vs DIBL: What Changes and What to Compare
Separate length-dependent threshold roll-off from drain-bias-induced barrier lowering, then connect each question to a process map.
Dark Current vs Read Noise: Separate Charge and Readout
Separate mean dark signal, dark-current shot noise and read noise when interpreting CMOS sensor behavior.
Electrical vs Optical Crosstalk: Where Did the Signal Move?
Use photon absorption to distinguish optical-path mixing from carrier-collection crosstalk in CMOS image sensors.
Gate Work Function vs Channel Doping in Threshold Control
Understand how gate work function and channel doping affect different parts of MOS threshold electrostatics.
High-k Gate Dielectrics: Capacitance Is Not Leakage
Separate gate capacitance, equivalent oxide thickness and leakage when comparing high-k dielectric stacks.
Interface Traps vs Fixed Charge: Different MOS Responses
Separate persistent charge contributions from dynamic interface-trap response in MOS devices.
Isolation vs Junction Leakage: Trace the Unwanted Current
Trace unwanted current paths to distinguish isolation-related and junction leakage without assuming they are exclusive.
STI vs DTI in Image Sensors: Trace the Isolation Path
Compare STI and DTI by tracing the electrical and optical paths that an image-sensor boundary must control.
14nm Fin Recess Integration: Mechanisms, Physics, and Process Control
Function in the Complete Flow In advanced multi-gate architectures, the transition from planar field-effect transistors to three-dimensional structures represents a fundamental…
14nm RMG Tungsten Gate CMP: Physical Mechanisms, Surface Chemistry, and Integration Logic
Function in the Complete Flow In advanced 14nm FinFET manufacturing, the replacement metal gate (RMG) integration scheme replaces sacrificial dummy gate materials with…
28nm Metal Gate CMP Mechanism: Principles, Dishing Control, and Integration Logic
Function in the Complete Flow In advanced planar CMOS technology, the replacement metal gate (RMG) integration scheme was introduced to preserve high-k gate dielectric integrity…
28nm Poly Gate Patterning Process Flow: Principles, Photolithography, and Etch Integration
Function in the Complete Flow In the 28nm Planar process flow, the gate patterning module acts as the central structural bridge between thin-film stack deposition and front-end…