Controlling Surface Topography in Advanced BEOL: The Physics and Process Principles of Copper Dishing and Erosion

Introduction

In modern integrated circuit manufacturing, back-end-of-line (BEOL) metallization is responsible for routing electrical signals across billions of transistors [P2]. To minimize electrical resistance and mitigate electromigration, the semiconductor industry transitioned from subtractive aluminum etching to the copper dual damascene process [P2], [T2]. Because copper cannot be easily patterned via conventional dry etching, trenches and vias are first etched into the dielectric layer, followed by barrier and copper deposition, and finally global planarization [T2].

This global planarization is achieved via chemical mechanical planarization (CMP) [P1]. While CMP is exceptionally effective at delivering nanometer-scale flatness over large wafer areas, it introduces severe, pattern-dependent topographical artifacts known as copper dishing and dielectric erosion [P1], [P2].

• Dishing is defined as the thickness loss of the copper line relative to the adjacent patterned dielectric [P1].
• Erosion represents the localized thinning of the dielectric material between metal lines relative to the unpatterned field oxide [P1].

Controlling copper dishing and erosion is critical for semiconductor yield and device reliability [P1]. Excessive topography variation limits the lithographic depth of focus (DOF) for subsequent levels, increases resistance-capacitance (RC) variations, and leads to catastrophic electrical shorts due to metallic residues [P1], [P2].

Physics & Mechanism

The fundamental physical principles of CMP combine contact mechanics, fluid dynamics, and interfacial electrochemistry [P1], [P3]. At its core, the material removal mechanism relies on a synergistic "chemical softening and mechanical shear" process [P3]. Slurry oxidizers react with the exposed copper to form a highly uniform, mechanically soft passivation layer, which is then removed by the mechanical action of slurry abrasive particles and the micro-asperities of the polishing pad [P3], [P5].

The Mechanism of Copper Dishing

Copper dishing is primarily driven by the differences in mechanical hardness and chemical removal rates between metallic copper and the surrounding dielectric material [P1], [P2], [T1]. Copper is a ductile metal that is significantly softer than traditional silicon dioxide or porous low-k dielectric films [P2], [T1]. Consequently, under a given downforce, the removal rate of copper is inherently higher than that of the dielectric [P1], [P2].

During CMP, the polishing pad behaves as an elastic, semi-rigid membrane [T1], [T2]. As it sweeps across the wafer surface under downward pressure, the pad deforms and sags into the softer copper features [T1]. This localized deflection allows the pad's asperities and slurry abrasives to continue abrading the copper even after it has been planarized to the level of the dielectric boundary [T1]. This deflection is geometrically worse in wider metal lines, resulting in a characteristic curved, cylindrical dishing profile where the center of the line experiences the greatest thickness loss [P2], [T1].

Mathematically, dishing is defined as: $$\text{Dishing} = H_{\text{oxide,pattern}} - H_{\text{Cu}}$$ where $H_{\text{Cu}}$ represents the height of the copper line surface and $H_{\text{oxide,pattern}}$ is the height of the adjacent patterned dielectric surface [P4].

The Mechanism of Dielectric Erosion

While dishing is a localized defect occurring within individual metal lines, dielectric erosion is a global, pattern-dependent wear phenomenon [P1]. Erosion occurs in regions with high pattern density and narrow dielectric spaces [P1].

From a contact mechanics perspective, the polishing pad cannot deform fully into extremely narrow dielectric spaces between dense metal lines [P1]. Consequently, the local contact pressure becomes highly concentrated on these thin dielectric fins [P1]. Under this elevated local pressure, the mechanical wear rate of the dielectric increases dramatically [P1]. Longer over-polishing times—required to ensure complete copper clearing across varying pattern densities—further accelerate this localized dielectric wear [P1].

Erosion is mathematically defined as: $$\text{Erosion} = H_{\text{oxide,field}} - H_{\text{oxide,pattern}}$$ where $H_{\text{oxide,field}}$ represents the unpatterned field oxide height far from the dense interconnect array [P4].

Process Principles

Optimizing a copper CMP process to minimize dishing and erosion requires balancing several process and material variables [P2]. Engineers must directionally tune these variables to maintain high material removal rates while mitigating pad deformation and localized wear [P5].

Downforce and Pad Properties

According to classical wear theory and Preston's law, the material removal rate scales proportionally with the applied downforce and relative velocity (Engineering Practice). However, in copper CMP, increasing the downward pressure directionally worsens dishing and erosion [P1], [P2]. Higher pressure forces the elastic polishing pad to deform more deeply into the copper trenches, increasing dishing [T1].

To combat pad deformation, process engineers utilize rigid polishing pads [T1]. A highly rigid pad maintains global planarity and resists sagging into wide metal features, thereby minimizing dishing [T1]. However, a pad that is too rigid cannot conform to wafer-scale bow or thickness non-uniformities, which leads to poor across-wafer uniformity [T1]. Thus, a carefully engineered semi-rigid pad with regular in-situ pad conditioning is employed to balance local planarity with global uniformity [P1], [T1].

Slurry Chemistry and Selectivity

The chemical formulation of the slurry is the primary knob for controlling the balance between copper dissolution and surface passivation [P5]. Copper CMP slurries typically contain:

1 [P3]. Oxidizers: Create a thin passivation film on the copper surface [P5]. 2. Chelating/Complexing Agents: Solubilize the oxidized copper ions and facilitate removal [P5]. 3. Corrosion Inhibitors: Adsorb onto the copper surface to protect low-pressure, recessed regions from static etching [P5].

To achieve highly efficient planarization, modern slurries must exhibit non-Prestonian behavior [P5]. This is often achieved by blending inhibitors of varying adsorption strengths [P5]. Under high pressure (at high topography features), the mechanical action of the abrasives readily breaks the inhibition layer, leading to high removal rates [P5]. In contrast, in low-pressure regions (within recessed trenches), the strong passivation film remains intact, suppressing static dissolution and significantly reducing dishing [P5].

Furthermore, the slurry's selectivity—the ratio of the copper removal rate to that of the barrier metal and the dielectric—must be carefully optimized [P1], [P6]. A slurry with extremely high selectivity toward copper will successfully clear bulk copper but will cause severe dishing if the over-polish step is extended [T1]. Conversely, low selectivity accelerates dielectric erosion, highlighting the need for multi-step CMP processes where the slurry chemistry is changed dynamically between bulk removal, barrier clearing, and over-polishing steps [P5].

Challenges & Failure Modes

When dishing and erosion are not controlled, they degrade both the electrical performance and the yield of advanced integrated circuits [P1], [P2].

Interconnect Resistance and RC Delay

The most direct consequence of dishing is the reduction of the effective cross-sectional area of the copper interconnect [P2]. Because electrical resistance is inversely proportional to the conductive cross-sectional area, dishing directly causes an increase in interconnect sheet resistance [P2], [P4]. This resistance spike degrades signal propagation speeds and increases RC delay, particularly in long, wide global interconnects where dishing is most severe [P2].

Dielectric Breakdown and Leakage

Severe dielectric erosion causes local thinning of the low-k dielectric or oxide layer separating adjacent metal lines [P1]. When the spacing between metal lines is reduced, the local electric field strength increases under bias [P2]. In fragile low-k or ultra-low-k dielectrics, this elevated electric field leads to higher leakage currents and accelerates time-dependent dielectric breakdown (TDDB), threatening the long-term reliability of the chip (Engineering Practice).

Metal Residues and Electrical Shorts

During CMP, variations in pattern density across the die can cause uneven clearing of the overburden copper [P1]. If the over-polish window is too short, metal residues (either copper or the underlying barrier metal, such as TaN or Ti) may remain on top of the eroded dielectric, causing catastrophic electrical shorts between adjacent lines [P1], [P3]. Conversely, if the over-polish step is extended to guarantee complete residue clearance, dishing and erosion are severely exacerbated in high-density regions [P1].

Trenching and Edge Recesses

Along the boundaries of wide copper lines, a localized defect known as "trenching" (or "fangs") can occur [P3]. This is characterized by sharp vertical gouges in the dielectric adjacent to the metal edge, driven by localized high shear stresses at the material boundary during polishing [P3]. Additionally, post-CMP cleaning chemistries can chemically attack this boundary, resulting in a "recess"—a sharp vertical step at the metal edge that compromises subsequent barrier and seed layer coverage [P1].

Technology Node Evolution

The management of copper dishing and erosion has evolved dramatically as the industry scaled from planar transistors to complex three-dimensional architectures [P2].

The Mature Era: 28nm Planar Nodes

At the 28nm Planar Flow node, standard copper CMP processes were manageable using moderately rigid pads and conventional slurries because interconnect aspect ratios were relaxed and dielectric films were mechanically robust [P1]. Topography variations were largely addressed by establishing standard layout coverage rules [P1].

The FinFET Era: 14nm to 7nm Nodes

As the industry transitioned to the 14nm FinFET and 7nm FinFET nodes, pitch scaling accelerated and mechanically fragile ultra-low-k dielectrics were introduced [P1], [P5]. The porous nature of these dielectrics made them highly susceptible to mechanical delamination and cracking under high polishing shear stress [P5].

To prevent delamination, process engineers transitioned to ultra-low downforce CMP [P5]. Because mechanical removal rates are reduced at lower pressures, slurry chemistry had to become highly chemical-dominant [P5]. Advanced slurries incorporating composite inhibitors were developed to maintain high removal rates on high features while preserving exceptionally strong passivation in recesses to prevent dishing [P5].

Furthermore, foundries introduced highly restrictive design rules [P1]. These rules mandate the insertion of dummy metal features (dummy fills) to ensure local pattern density is uniform across the entire die [P1]. By balancing the metal-to-dielectric ratio, dummy fills distribute the mechanical load evenly across the polishing pad, effectively suppressing both dishing and erosion [P1], [P6].

Related Processes

CMP does not operate in isolation; its success is highly dependent on upstream and downstream process integration [P3].

• Lithography and Dry Etching: The initial trenches and vias are defined using high-precision photolithography—such as extreme ultraviolet lithography—and anisotropic dry etching [P2], [T2]. Any non-uniformity in the etch depth or trench profile directly translates to local variations in copper volume, which complicates the subsequent CMP step [P1].
• Barrier and Seed Deposition: Prior to copper electroplating, a thin barrier layer (typically TaN or TiN) and a copper seed layer are deposited [P6]. In advanced sub-10nm nodes, atomic layer deposition (ALD) is frequently used to deposit ultra-thin, highly conformal barrier layers [T2]. The mechanical adhesion of this ALD barrier interface is critical; if the adhesion is weak, the high shear forces during CMP will cause film delamination at the trench boundaries [P1].

Future Outlook

As device scaling pushes beyond the 3nm node, conventional copper metallization is reaching its physical limits [P2]. At extremely narrow line widths, the resistivity of copper increases exponentially due to electron scattering at the grain boundaries and interfaces [P4].

To bypass these limits, the industry is actively exploring alternative metals such as Cobalt (Co) and Ruthenium (Ru) (Engineering Practice). From a planarization perspective, these metals possess significantly higher mechanical hardness than copper (Engineering Practice). Their high hardness dramatically reduces their susceptibility to pad-induced deformation and dishing, potentially widening the CMP process window [P5].

Additionally, researchers are investigating selective area ALD for bottom-up metallization (Engineering Practice). By growing metal selectively within the trenches, the overburden can be minimized or eliminated entirely, pointing toward a future where the challenges of copper dishing and erosion are solved by advanced chemical synthesis rather than mechanical abrasion [P2].