14nm FinFETPreview

The 14nm FinFET process represents a landmark inflection point in semiconductor manufacturing, marking the broad industry transition from planar bulk CMOS to three-dimensional transistor architectures. At this node, classical scaling of gate length and oxide thickness alone could no longer deliver acceptable electrostatic control over the channel, driving the adoption of the fin-shaped field-effect transistor (FinFET) as the dominant device architecture.

In a FinFET, the channel is formed in a narrow, vertically-oriented silicon fin that protrudes above the substrate. The gate electrode wraps around three sides of this fin — top and both sidewalls — creating a tri-gate or quasi-planar electrostatic environment that dramatically improves gate control over the channel potential. This geometry suppresses short-channel effects such as drain-induced barrier lowering (DIBL) and subthreshold slope degradation that plagued planar devices at equivalent gate lengths. The 14nm node typically achieves fin widths well below the lithographic resolution limit through sidewall image transfer (SIT) patterning, and integrates a high-κ metal gate (HKMG) stack in a replacement metal gate (RMG) flow. The resulting process involves approximately 362 discrete fabrication steps organized into tightly coupled modules spanning the full FEOL–MOL–BEOL stack.

Front-End-of-Line (FEOL)

The FEOL encompasses all steps from substrate preparation through transistor formation, and at the 14nm node this is dominated by fin patterning, isolation engineering, and gate stack integration.

Fin Definition and Isolation