14nm FinFETPreview

ctively etched using anisotropic plasma processes [P1][P2]. Without this Stop Oxide, the halogen-based chemistry used to pattern the a-Si mandrel would aggressively attack and deplete the underlying Pad Nitride, leading to severe profile variations in the final fin structures [P1]. Thus, this step ensures high-selectivity pattern transfer, maintaining the integrity of the pad nitride/pad oxide stack which serves to safeguard the underlying active silicon substrate [P1][T3].

This step typically employs plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) to deposit a highly uniform and dense silicon dioxide ($SiO_2$) film [P1][A1]. The core mechanism of chemical deposition involves precursor transport to the substrate, adsorption on the pad nitride surface, and subsequent chemical reactions driven by thermal energy or plasma activation [P1][A1]. For ALD-based processes, the film growth operates via self-limiting, sequential surface reactions, where organosilicon precursors saturatedly chemisorb onto surface hydroxyl groups, followed by an oxidation step (e.g. [P1], using $O_2$ plasma or ozone) that abstracts ligands and reconstructs the oxide network [P1]. The plasma excitation provides non-thermal energy that allows the reaction to overcome thermodynamic barriers at low temperatures, ensuring high density and minimal thermal budget [P1][T2]. The resulting silicon dioxide film exhibits an extremely low wet and dry etch rate in subsequent silicon-selective etches, serving as a reliable physical barrier that effectively terminates the a-Si etch process at the precise oxide-silicon interface [P1][T3].

Silicon dioxide ($SiO_2$) is selected as the stop layer material because of its exceptional etch selectivity relative to silicon and silicon nitride in fluorine- or bromine-based dry etching environments [P1][T3]. The deposition method must balance throughput, film stress, and conformality (Engineering Practice). PECVD is often selected for its superior deposition rate and ability to tune film stress by adjusting radio frequency (RF) power, gas flow ratios (e.g. [P1], $SiH_4$/$N_2O$ or TEOS/$O_2$), and substrate temperature [P1][A1]. The interaction of these parameters is crucial: increasing RF power and substrate temperature enhances film density and lowers the wet etch rate, but must be balanced to prevent thermal-induced stress or cracking in the underlying pad nitride layer [P1][A1]. Conversely, lower temperatures prevent dopant diffusion and stress-induced defects, but can lead to higher hydrogen incorporation, reducing chemical resistance and compromising the etch-stop performance [P1][P2].

In a 14nm FinFET flow, "Stop Oxide Deposition" is highly distinct from subsequent steps like S/D Thin Oxide & HM Deposition, POP Oxide Liner Deposition, or PMD1 Hard Oxide Deposition, which serve thermal, strain, or isolation functions post-fin formation [P3][T2]. In the 14nm node, the fin pitch is aggressively scaled, requiring sub-nanometer control of the fin height and width to prevent short-channel effects and threshold voltage variability [P1][P2]. The Stop Oxide must be extremely thin yet highly uniform to prevent "pitch walking" and profile asymmetry during the double patterning process (Engineering Practice). Any non-uniformity in this early-stage oxide deposition would propagate down to the final silicon fin geometry, directly impacting the electrostatic control and parasitics of the completed 14nm FinFET devices [P1][T1].