Pad Nitride Deposition - 14nm FinFET 14nm

During deposition, the thermal energy drives the desorption of hydrogen and chlorine species, promoting dense Si-N network formation, which inherently introduces high tensile intrinsic stress within the deposited film .

The pad oxide grown in the preceding step acts as a critical strain and stress buffer layer to prevent mechanical defects (such as cracks, dislocations, or stacking faults) from propagating into the underlying silicon substrate due to the high intrinsic tensile stress of the s

ilicon nitride film . The pad nitride deposited in this step serves multiple critical integration functions within the 14nm FinFET patterning flow (Engineering Practice). First, it acts as a robust hardmask for subsequent shallow trench isolation (STI) silicon etching . Second, it functions as an oxidation barrier mask that prevents the top active silicon areas from oxidizing during subsequent high-temperature thermal steps . Third, it acts as a highly selective polishing stop layer during the subsequent STI chemical-mechanical planarization (CMP) process to protect the active silicon channel . Following this step, the flow proceeds to Stop Oxide Deposition and a-Si Hardmask Deposition, which prepare the wafer for sub-lithographic patterning to define the vertical fins (Engineering Practice).

The thermal deposition of pad nitride is typically executed via Low-Pressure Chemical Vapor Deposition (LPCVD) . The core chemical mechanism involves the thermal decomposition and reaction of dichlorosilane (SiH2Cl2) and ammonia (NH3) at elevated temperatures in a vertical furnace (Engineering Practice). This reaction yields stoichiometric silicon nitride (Si3N4), while releasing hydrochloric acid (HCl) and hydrogen (H2) as volatile gaseous byproducts (Engineering Practice). Because LPCVD operates in a surface-reaction-rate-limited regime, it ensures excellent step coverage, high film density, and exceptional thickness uniformity across the wafer (Engineering Practice). During deposition, the thermal energy drives the desorption of hydrogen and chlorine species, promoting dense Si-N network formation, which inherently introduces high tensile intrinsic stress within the deposited film .

LPCVD thermal deposition is selected over Plasma-Enhanced Chemical Vapor Deposition (PECVD) because the thermally grown LPCVD films possess superior density, a lower wet etch rate, and higher chemical resistance during subsequent patterning steps . Process parameter interaction directions must be carefully optimized to manage film quality and mechanical stress . Raising the deposition temperature accelerates the surface reaction kinetics and enhances hydrogen desorption, which increases the film density and chemical resistance but also increases the intrinsic tensile stress and potential for wafer bow (Engineering Practice). Conversely, reducing the thermal deposition temperature lowers the intrinsic stress, but results in a less dense film containing higher hydrogen impurities, which increases its susceptibility to premature erosion during subsequent phosphoric acid wet etches and CMP steps (Engineering Practice). The flow ratio of dichlorosilane to ammonia must also be balanced, as a silicon-rich film reduces tensile stress but suffers from a higher etch rate in selective wet chemistries, whereas a nitrogen-rich film maximizes etch resistance at the expense of higher cracking risks (Engineering Practice).

At the 14nm FinFET node, where the active area is composed of high-aspect-ratio 3D vertical fins rather than planar substrates, managing film stress and thickness uniformity is paramount (Engineering Practice). Localized mechanical stress originating from the pad nitride can induce silicon dislocation loops along the <111> slip planes, leading to severe stress-induced leakage current (SILC) and standby power degradation . Furthermore, because subsequent stop oxide and amorphous silicon hardmasks are deposited on this stack to enable self-aligned double patterning (SADP), any thickness variation or localized stress in the pad nitride can translate to vertical profile distortion, such as fin bending or line-edge roughness (Engineering Practice). Thus, achieving an ultra-uniform, low-stress thermal LPCVD pad nitride is a prerequisite for achieving robust electrostatic gate control and uniform sub-14nm fin dimensions (Engineering Practice).

[High] Stress-Induced Dislocation Formation and Junction Leakage: The high intrinsic tensile stress of stoichiometric LPCVD silicon nitride films can generate immense mechanical stress concentrated at the active edge interfaces . If the pad oxide buffer is too thin, or if the thermal budget is poorly controlled, this stress induces silicon dislocation propagation along the <111> slip planes . When these crystalline defects intersect the junction depletion regions of the 14nm FinFETs, they act as high-conductivity paths that significantly increase stress-induced leakage current (SILC) and degrade standby power .
[High] Film Cracking and Wafer Bow: Due to the high intrinsic tensile stress of stoichiometric silicon nitride, tensile strain scales with the thickness of the deposited film . If the deposition is performed without stress mitigation steps, the accumulated stress can exceed the critical fracture toughness of the material, leading to film cracking . This stress also induces severe wafer warpage, which prevents proper electrostatic chucking during subsequent photolithography and reactive ion etching, leading to focus degradation and wafer-handling failures .
[Medium] Incomplete Oxide Etch Stop and Substrate Damage: During the subsequent hardmask patterning, the pad nitride must be selectively etched using reactive ion etching (RIE) without punching through the thin underlying pad oxide . If the nitride thickness uniformity is poor, or if the RIE process lacks sufficient selectivity over silicon dioxide, the overetch step will consume the pad oxide and expose the active silicon substrate . This exposure leads to direct physical ion bombardment damage and chemical contamination in the active fin area, which degrades subthreshold swing and gate oxide reliability .
[Medium] Nitride Erosion and Active Dishing during STI CMP: The pad nitride acts as the primary polish stop layer during the subsequent STI chemical-mechanical planarization (CMP) process . If the nitride film is deposited with sub-stoichiometric density due to excessive hydrogen retention or low deposition temperatures, its mechanical hardness and chemical resistance are compromised . This leads to accelerated nitride erosion during CMP overpolishing, causing dishing of the trench oxide fill, variation in the active fin heights, and poor threshold voltage control across the die .

[High] Stress-Induced Dislocation Formation and Junction Leakage: The high intrinsic tensile stress of stoichiometric LPCVD silicon nitride films can generate immense mechanical stress concentrated at the active edge interfaces . If the pad oxide buffer is too thin, or if the thermal budget is poorly controlled, this stress induces silicon dislocation propagation along the <111> slip planes . When these crystalline defects intersect the junction depletion regions of the 14nm FinFETs, they act as high-conductivity paths that significantly increase stress-induced leakage current (SILC) and degrade standby power .
[High] Film Cracking and Wafer Bow: Due to the high intrinsic tensile stress of stoichiometric silicon nitride, tensile strain scales with the thickness of the deposited film . If the deposition is performed without stress mitigation steps, the accumulated stress can exceed the critical fracture toughness of the material, leading to film cracking . This stress also induces severe wafer warpage, which prevents proper electrostatic chucking during subsequent photolithography and reactive ion etching, leading to focus degradation and wafer-handling failures .
[Medium] Incomplete Oxide Etch Stop and Substrate Damage: During the subsequent hardmask patterning, the pad nitride must be selectively etched using reactive ion etching (RIE) without punching through the thin underlying pad oxide . If the nitride thickness uniformity is poor, or if the RIE process lacks sufficient selectivity over silicon dioxide, the overetch step will consume the pad oxide and expose the active silicon substrate . This exposure leads to direct physical ion bombardment damage and chemical contamination in the active fin area, which degrades subthreshold swing and gate oxide reliability .
[Medium] Nitride Erosion and Active Dishing during STI CMP: The pad nitride acts as the primary polish stop layer during the subsequent STI chemical-mechanical planarization (CMP) process . If the nitride film is deposited with sub-stoichiometric density due to excessive hydrogen retention or low deposition temperatures, its mechanical hardness and chemical resistance are compromised . This leads to accelerated nitride erosion during CMP overpolishing, causing dishing of the trench oxide fill, variation in the active fin heights, and poor threshold voltage control across the die .

14nm FinFETPreview

Process Cross-Section

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Risks & Challenges

14nm FinFETPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges