Amorphous silicon is deposited as a sacrificial mandrel in SADP to enable high-selective removal without damaging adjacent dielectrics .
In depth
In the 14nm FinFET node, direct photolithography cannot resolve the sub-30nm fin pitches required for physical density scaling, necessitating multi-patterning schemes such as Self-Aligned Double Patterning (SADP) . The previous steps establish a protective stack consisting of pad oxide, pad nitride, and stop oxide over the bulk silicon substrate [P
2]. The amorphous silicon (a-Si) hardmask deposited in this step acts as a temporary sacrificial mandrel layer, which will be patterned via the subsequent CSOH, SiON, and Fin Mandrel (FNM) lithography steps (Engineering Practice). The a-Si layer is designed to receive the high-fidelity photoresist patterns and spacer depositions, eventually translating these into ultra-dense, vertical fin geometries with minimized line-edge roughness to optimize electrostatic gate control and suppress short-channel effects .
Amorphous silicon deposition typically utilizes Plasma-Enhanced Chemical Vapor Deposition (PECVD) or Low-Pressure Chemical Vapor Deposition (LPCVD) based on silane precursor pyrolysis . At elevated temperatures, the thermal energy decomposes precursor gases into silicon-bearing radicals and molecular hydrogen . These reactive radicals adsorb onto the stop oxide surface and undergo surface diffusion, migration, and subsequent nucleation to form an amorphous silicon network lacking long-range crystalline order . Maintaining low substrate temperatures relative to polycrystalline silicon deposition preserves the amorphous state by limiting surface adatom mobility and preventing thermal crystallization . The presence of hydrogen within the plasma or precursor stream can passivate dangling bonds in the growing film, which modifies the film's density, refractive index, and chemical etch resistance .
a-Si is selected because of its exceptional dry etch selectivity against silicon dioxide and silicon nitride hardmasks, which is essential during anisotropic pattern transfer into the underlying stop oxide and pad layers . This step-coverage and etch-rate behavior can be modulated by adjusting deposition chamber pressure, precursor flow ratios, and plasma RF power . Higher RF power or substrate temperature enhances the kinetic energy of species, driving film densification but risking crystallization into polysilicon or inducing thermal stress that can cause wafer warp . Unlike PECVD SiN or PEALD Oxide hardmasks, a-Si can be highly selectively stripped using wet basic solutions or highly selective radical-based dry etching without attacking the adjacent spacer dielectrics, making it an ideal sacrificial mandrel in SADP flows .
At the 14nm FinFET node, control over fin width variation is exceptionally stringent, as variations directly impact the threshold voltage and drive current uniformity . Any grain boundary present in a crystalline silicon hardmask would transfer local line-edge roughness (LER) to the underlying fin during dry etching . The amorphous nature of the a-Si hardmask eliminates these grain-boundary-induced edge irregularities, ensuring an atomically smooth hardmask sidewall (Engineering Practice). This isotropic smoothness is critical for mitigating local electric field concentrations and preventing variability in short-channel effect suppression across dense arrays .
Risks & Challenges
[High] Localized Crystallization (Grain Formation): If the deposition temperature exceeds the crystallization threshold or if subsequent thermal steps provide excessive thermal budget, the amorphous silicon film can undergo local phase transitions to a crystalline phase . This crystallization introduces grain boundaries, which exhibit different etch rates compared to the amorphous matrix, leading to severe line-edge roughness (LER) and line-width roughness (LWR) during subsequent pattern transfer steps .
[Medium] Excessive Film Stress and Delamination: High RF power or improper precursor diluent ratios during deposition can result in high compressive or tensile intrinsic stress in the a-Si film . Since the film is deposited on a stop oxide layer, high mechanical stress can exceed the adhesion strength at the a-Si/oxide interface, causing peeling, delamination, or wafer warpage that compromises downstream lithographic depth of focus .
[Medium] Hydrogen Outgassing and Micro-voiding: Low-temperature PECVD of a-Si typically incorporates significant concentrations of hydrogen within the amorphous network (Engineering Practice). During subsequent high-temperature processing steps in the flow, this trapped hydrogen can outgas, causing bubble formation, localized film blistering, or micro-voids that degrade the hardmask pattern fidelity during downstream etch steps .
[Low] Edge-to-Center Etch Rate Non-uniformity: Spatial variations in plasma density or temperature across the wafer stage during PECVD can lead to variations in a-Si film density and hydrogen content . This density non-uniformity alters the chemical resistance of the hardmask, resulting in non-uniform etch rates during the mandrel etch and subsequent fin pattern transfer, ultimately causing fin height and width variations across the wafer .
A free account opens the full rationale, risk analysis, and the paper and patent citations behind them.