Amorphous silicon is deposited as a sacrificial mandrel in SADP to enable high-selective removal without damaging adjacent dielectrics [P3].
In the 14nm FinFET node, direct photolithography cannot resolve the sub-30nm fin pitches required for physical density scaling, necessitating multi-patterning schemes such as Self-Aligned Double Patterning (SADP) [P3][A1]. The previous steps establish a protective stack consisting of pad oxide, pad nitride, and stop oxide over the bulk silicon substrate […
Read the full explanation and sources for free.
Sign Up Free