14nm FinFET

In the 14nm FinFET patterning module, the vertical fins are defined using a multi-layer hardmask stack that undergoes advanced lithography and anisotropic etching [P1][P2]. To initiate this patterning stack, a robust silicon nitride layer (Pad Nitride) is deposited to serve as both an etch mask and a chemical mechanical planarization (CMP) stop layer [P4]. However, directly depositing silicon nitride on the bare silicon substrate induces severe mechanical strain due to the high intrinsic tensile…

• [High] Stress-Induced Crystalline Dislocations: If the pad oxide is grown too thin, it cannot adequately buffer the massive intrinsic tensile stress exerted by the subsequent LPCVD silicon nitride film [T1][P4]. This high mechanical shear stress exceeds the critical resolved shear stress of silicon at high deposition temperatures, leading to the generation of crystalline dislocations and slip planes in the silicon substrate [T1][A1]. These defects propagate into the active fin channel, act…