Pad Oxide Growth - 14nm FinFET 14nm

The growth of the pad oxide is achieved via dry thermal oxidation, where the substrate is exposed to oxygen gas at elevated temperatures .

In the 14nm FinFET patterning module, the vertical fins are defined using a multi-layer hardmask stack that undergoes advanced lithography and anisotropic etching . To initiate this patterning stack, a robust silicon nitride layer (Pad Nitride) is deposited to serve as both an etch mask and a chemical mechanical planarization (CMP) stop layer .

However, directly depositing silicon nitride on the bare silicon substrate induces severe mechanical strain due to the high intrinsic tensile stress of the chemical vapor deposition (CVD) nitride film . This high interface stress can generate crystalline dislocations, defect propagation, and cracking in the underlying silicon lattice . To prevent this structural degradation, a thin "pad oxide" is thermally grown on the substrate before the nitride deposition . The pad oxide acts as a critical strain buffer, accommodating the shear stress through viscoelastic relaxation and preventing defect formation in the silicon active region .

The growth of the pad oxide is achieved via dry thermal oxidation, where the substrate is exposed to oxygen gas at elevated temperatures . The physical mechanism of this process is governed by the classic Deal-Grove model, describing a multi-step transport and reaction sequence . Oxidant molecules ($O_2$) transport from the bulk gas to the wafer surface, diffuse through the growing silicon dioxide layer, and chemically react with silicon atoms at the $Si/SiO_2$ interface . The chemical reaction is represented as $Si(solid) + O_2(gas) \rightarrow SiO_2(solid)$ (Engineering Practice). For the ultra-thin pad oxide regime, the growth rate is controlled by the surface reaction rate rather than diffusion, exhibiting a linear thickness-to-time relationship . As the oxidation reaction proceeds, it consumes silicon from the substrate, and the volume expansion (associated with a Pilling-Bedworth ratio of approximately 2.2) generates compressive stress within the grown oxide layer . This thermal reaction yields an exceptionally clean, stable interface with a very low density of interface states ($D_{it}$) .

Dry thermal oxidation is selected over wet thermal oxidation because dry-grown oxides are denser, have a lower wet etch rate, and exhibit superior thickness uniformity . The oxidation is performed in a vertical thermal furnace to ensure uniform thermal distribution and gas flow (Engineering Practice). The key parameters controlling this process are the oxidation temperature, oxidation time, and the partial pressure of the $O_2$ oxidant . Higher process temperatures exponentially increase both the linear and parabolic rate constants by overcoming the activation energy barrier for diffusion and reaction . However, thermal budget constraints in advanced nodes require minimizing high-temperature exposure to prevent premature dopant diffusion or structural relaxation . To achieve highly controllable and uniform growth of ultra-thin films, the oxidant gas is typically diluted with an inert carrier gas (such as $N_2$), which reduces the oxidant partial pressure and slows down the initial rapid linear growth phase .

For the 14nm FinFET technology node, the pad oxide thickness must be scaled down and optimized with sub-nanometer precision to prevent short-channel effects and threshold voltage variation . The subsequent pad nitride and stop oxide layers must precisely define the fin topography and protect the fin tops during high-aspect-ratio shallow trench isolation (STI) filling and recess processes . If the pad oxide is grown too thick, it enhances lateral diffusion of oxygen during subsequent processing or etchants (like HF) during cleaning, leading to the classic 'bird's beak' encroachment . This lateral encroachment consumes active silicon at the fin corners, resulting in severe variations in the effective fin height ($H_{fin}$) and fin width ($W_{fin}$) . Conversely, a pad oxide that is too thin cannot sufficiently relax the intrinsic stress of the pad nitride layer, causing stress-induced bandgap changes or dislocation defects that degrade carrier mobility . Thus, the pad oxide growth process in 14nm FinFETs is a critical trade-off between stress-buffering capacity and dimensional control of the 3D fin structure .

[High] Stress-Induced Crystalline Dislocations: If the pad oxide is grown too thin, it cannot adequately buffer the massive intrinsic tensile stress exerted by the subsequent LPCVD silicon nitride film . This high mechanical shear stress exceeds the critical resolved shear stress of silicon at high deposition temperatures, leading to the generation of crystalline dislocations and slip planes in the silicon substrate . These defects propagate into the active fin channel, acting as generation-recombination centers that severely increase off-state junction leakage and degrade carrier mobility in the FinFET device .
[Medium] Lateral Encroachment and Fin Profile Variation: If the pad oxide is grown too thick or has low density, it provides an easy, high-diffusivity path for oxidants during subsequent thermal oxidation steps or acts as a fast-etch pathway during subsequent wet chemical etching steps . The oxidant or etchant penetrates laterally under the pad nitride mask, causing localized oxidation or etching of the silicon at the fin corners . This leads to variations in the effective fin height ($H_{fin}$) and fin width ($W_{fin}$), which directly shifts the threshold voltage ($V_{th}$) and degrades subthreshold swing (SS) due to localized electrostatic variation .
[Medium] Surface Contamination and Interface Traps: Prior to pad oxide growth, any native oxide, organic contaminants, or chemical impurities left on the silicon wafer surface can become incorporated into the growing oxide layer or trapped at the $Si/SiO_2$ interface . Because dry thermal oxidation consumes silicon from the substrate, it can drive these impurities deeper, resulting in high interface trap density ($D_{it}$) and fixed oxide charge . While this is a dummy oxide stack eventually removed, these interface traps and defects can cause localized mechanical weak points, resulting in pit formation or surface roughness on the silicon during subsequent strip steps, which ultimately degrades the channel mobility of the formed fins .
[Low] Thickness Non-Uniformity due to Crystal Orientation Effects: Thermal oxidation rates of silicon are highly dependent on the crystallographic orientation of the silicon surface, with the (111) plane oxidizing faster than the (100) plane due to higher areal density of silicon atoms available for reaction . In 14nm FinFET fabrication, if the starting substrate has patterned features or surface roughness exposing multiple crystal facets, the pad oxide thickness will vary locally . This non-uniformity in pad oxide thickness leads to variation in the stress-buffering capability across the wafer, resulting in localized defect generation and non-uniform hardmask etching profiles during the subsequent FIN_PATTERN module steps .

The growth of the pad oxide is achieved via dry thermal oxidation, where the substrate is exposed to oxygen gas at elevated temperatures .

[High] Stress-Induced Crystalline Dislocations: If the pad oxide is grown too thin, it cannot adequately buffer the massive intrinsic tensile stress exerted by the subsequent LPCVD silicon nitride film . This high mechanical shear stress exceeds the critical resolved shear stress of silicon at high deposition temperatures, leading to the generation of crystalline dislocations and slip planes in the silicon substrate . These defects propagate into the active fin channel, acting as generation-recombination centers that severely increase off-state junction leakage and degrade carrier mobility in the FinFET device .
[Medium] Lateral Encroachment and Fin Profile Variation: If the pad oxide is grown too thick or has low density, it provides an easy, high-diffusivity path for oxidants during subsequent thermal oxidation steps or acts as a fast-etch pathway during subsequent wet chemical etching steps . The oxidant or etchant penetrates laterally under the pad nitride mask, causing localized oxidation or etching of the silicon at the fin corners . This leads to variations in the effective fin height ($H_{fin}$) and fin width ($W_{fin}$), which directly shifts the threshold voltage ($V_{th}$) and degrades subthreshold swing (SS) due to localized electrostatic variation .
[Medium] Surface Contamination and Interface Traps: Prior to pad oxide growth, any native oxide, organic contaminants, or chemical impurities left on the silicon wafer surface can become incorporated into the growing oxide layer or trapped at the $Si/SiO_2$ interface . Because dry thermal oxidation consumes silicon from the substrate, it can drive these impurities deeper, resulting in high interface trap density ($D_{it}$) and fixed oxide charge . While this is a dummy oxide stack eventually removed, these interface traps and defects can cause localized mechanical weak points, resulting in pit formation or surface roughness on the silicon during subsequent strip steps, which ultimately degrades the channel mobility of the formed fins .
[Low] Thickness Non-Uniformity due to Crystal Orientation Effects: Thermal oxidation rates of silicon are highly dependent on the crystallographic orientation of the silicon surface, with the (111) plane oxidizing faster than the (100) plane due to higher areal density of silicon atoms available for reaction . In 14nm FinFET fabrication, if the starting substrate has patterned features or surface roughness exposing multiple crystal facets, the pad oxide thickness will vary locally . This non-uniformity in pad oxide thickness leads to variation in the stress-buffering capability across the wafer, resulting in localized defect generation and non-uniform hardmask etching profiles during the subsequent FIN_PATTERN module steps .

14nm FinFETPreview

Process Cross-Section

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In depth

Risks & Challenges

14nm FinFETPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges