In bulk silicon configurations, the substrate undergoes thermal oxidation to grow a screen oxide, followed by high-energy well implantations to define the p-wells and n-wells .
In depth
The substrate preparation step is the initial baseline phase of the 14nm FinFET integration flow, establishing the physical, crystallographic, and electrical foundation for the entire device architecture . In the 14nm node, the starting substrate must provide an ultra-clean, defect-free single-crystalline surfa
ce to support subsequent high-aspect-ratio fin patterning . This step immediately precedes Pad Oxide Growth, Pad Nitride Deposition, and Stop Oxide Deposition, which collectively serve as the hard mask and stress-buffer stack for anisotropic silicon etching . The precise control of substrate doping, crystalline quality, and surface preparation directly influences the threshold voltage stability, subthreshold swing, and junction leakage of the finished FinFETs .
At the physical level, the selection of the substrate crystal orientation dictates the density of unsatisfied atomic bonds at the silicon-dielectric interface . A (100) crystal orientation is selected as the primary substrate plane because it exhibits significantly fewer dangling bonds and interface traps compared to other orientations when oxidized, optimizing carrier transport and gate dielectric reliability . In bulk silicon configurations, the substrate undergoes thermal oxidation to grow a screen oxide, followed by high-energy well implantations to define the p-wells and n-wells . During these implantations, physical channeling of ions through the open crystal channels is suppressed by tilting and rotating the substrate, ensuring a well-controlled, predictable dopant profile . Alternatively, Silicon-on-Insulator (SOI) substrates utilize a thin active silicon layer separated from the handle substrate by a buried oxide (BOX) layer, which structurally eliminates sub-fin leakage and minimizes parasitic junction capacitances .
Material and method selection for the 14nm node is guided by a trade-off between manufacturing cost, isolation performance, and channel mobility requirements . Bulk silicon substrates represent a highly cost-effective and mature platform but require complex retrograde well engineering and deep shallow trench isolation (STI) to suppress inter-device leakage . To mitigate metallic contamination introduced during handling, bulk substrates undergo intrinsic gettering, where high-temperature thermal cycles precipitate bulk interstitial oxygen to create a defect-free denuded zone near the active surface while trapping mobile metal impurities deep within the wafer bulk . For high-performance RF or logic applications, strained-silicon substrates are selected, where an epitaxial silicon layer is grown over a relaxed, vertically graded silicon-germanium (SiGe) buffer structure to induce lateral tensile strain . This lattice strain lifts the degeneracy of the silicon conduction band, reducing intervalley phonon scattering and decreasing the effective electron mass to substantially boost carrier mobility .
At the 14nm node, the starting substrate's global and local flatness is critically linked to lithographic depth-of-focus limitations during fin patterning . Any nanoscale spatial variation or micro-roughness on the starting substrate is amplified during subsequent reactive ion etching of the fins, leading to critical dimension variation and line-edge roughness . In platforms utilizing SiGe-on-insulator or strained channel architectures, maintaining film stress uniformity across the wafer is vital to prevent lattice relaxation and dislocation generation during downstream high-temperature thermal anneals .
Risks & Challenges
[High] Channeling Effects during Well Implantation: In bulk silicon substrates, high-energy ion implantation for well formation can experience severe ion channeling if the incident dopant beam aligns with the open crystallographic directions of the (100) silicon lattice, leading to deep, uncontrolled dopant tails and variable threshold voltages . This failure mode is mitigated by tilting the substrate relative to the ion beam and continuously rotating the wafer during implantation to randomize the ion trajectory relative to the crystal channels .
[Medium] Metallic Contamination and Active Area Junction Leakage: Trace transition metals (such as copper, iron, or nickel) can contaminate the substrate surface during early transport and processing steps, diffusing rapidly into the active device region during subsequent thermal cycles . These metals act as deep-level recombination centers within the depletion region, leading to elevated junction leakage currents and device failure, which requires the activation of bulk oxygen precipitates to act as intrinsic gettering sites deep within the substrate bulk .
[Medium] SOI Floating Body and Kink Effects: When utilizing Silicon-on-Insulator starting substrates to isolate the active region, the absence of a direct substrate contact leaves the active fin body electrically floating . Under high drain biases, impact ionization near the drain generates excess holes (in n-channel devices) that accumulate in the floating body, temporarily lowering the threshold voltage and creating an anomalous non-linear increase in drain current known as the kink effect .
[Low] Fin Bottom Oxidation and Structural Instability in SiGe Platforms: In high-mobility SiGe-on-insulator substrates, high-temperature processing steps can cause oxygen to diffuse through the buried oxide layer to the base of the patterned fins . The resulting localized oxidation of the SiGe fin base leads to structural volume expansion and high local stresses, which can cause fin lifting, warping, or catastrophic structural collapse .
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