PECVD forms a mechanically robust SiN hardmask, preserving pattern-transfer fidelity without compromising underlying device layers .
The PECVD SiN hardmask deposition in the CONTACT_SC module is introduced after formation of an oxide-based hardmask and before subsequent organic spin-on coating steps to provide a mechanically robust, plasma-resistant pattern transfer layer for contact definition in 14 nm FinFET integration . In this flow position,
the silicon nitride layer functions as a composite hardmask that enhances etch selectivity and profile fidelity when transferring fine contact features through underlying dielectric stacks, which is a requirement as contact critical dimensions approach lithographic limits at this node . The choice to deposit SiN after PEALD oxide hardmask deposition reflects an integration strategy where the conformal oxide provides interfacial coverage and stress buffering, while the overlying nitride supplies higher chemical durability against fluorocarbon and hydrogen-based plasmas used later in contact etching . This step also prepares a chemically compatible and mechanically stiff surface for the next spin-on carbon and spin-on oxide layers, ensuring uniform coating and minimizing pattern collapse during subsequent lithography and etch cycles .
PECVD silicon nitride deposition relies on non-equilibrium plasma physics in which energetic electrons dissociate silicon- and nitrogen-containing precursor gases into reactive radicals that drive film formation at the wafer surface . These radicals adsorb onto the surface and undergo surface-limited reactions that form a cross-linked Si–N network, while hydrogen is incorporated as Si–H and N–H bonds depending on plasma chemistry and surface reaction pathways . Because the plasma supplies activation energy independent of substrate heating, the process decouples film formation from thermal budget, enabling deposition after temperature-sensitive middle-of-line structures without inducing diffusion or stress relaxation in underlying layers . The balance between radical flux, ion bombardment, and surface mobility governs film density and microstructure, where increased radical-driven nitridation promotes etch resistance, while excessive ion energy can induce lattice damage and defect states at interfaces .
Silicon nitride is selected as the hardmask material due to its intrinsically high bond strength, low permeability, and superior resistance to both wet and dry etchants compared with most silicon oxides, which directly improves pattern transfer margin in dense contact arrays . PECVD is chosen over LPCVD because the latter requires temperatures incompatible with advanced FinFET MOL integration, while PECVD offers sufficient film quality when plasma chemistry is engineered to reduce hydrogen incorporation and improve network densification . From a parameter-interaction perspective, increasing nitrogen radical availability relative to silicon-containing species drives the film composition toward stoichiometric bonding, which enhances chemical durability but can increase intrinsic stress, whereas higher surface mobility promotes densification and reduced porosity at the expense of potential stress buildup . These directional trade-offs motivate tight process monitoring of plasma state and film properties to ensure the nitride hardmask meets both mechanical and integration requirements without compromising underlying device layers .
At the 14 nm technology node, contact patterning must contend with high-aspect-ratio topography created by fins, spacers, and replacement metal gate structures, making hardmask integrity a yield-critical factor . PECVD SiN at this node is engineered to balance conformality with directional deposition characteristics, accepting reduced step coverage compared with ALD in exchange for higher throughput and improved mechanical strength required for aggressive contact etches . Additionally, stress and hydrogen content in the nitride layer must be carefully managed to avoid fin deformation or interface state generation that could degrade contact resistance and device reliability, consistent with FinFET integration challenges reported in advanced contact schemes .
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