Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
Deep Dive into In-Situ Steam Generation (ISSG) in Semiconductor Processing: Physics, Kinetics, and Integration
In modern complementary metal-oxide-semiconductor (CMOS) fabrication, the synthesis of high-quality silicon dioxide ($\text{SiO}_2$) thin films with precise atomic-level control…
Engineering the Interfacial Bridge: Principles, Mechanisms, and Integration of Liner Layers in Advanced Semiconductor Manufacturing
In the intricate architecture of modern integrated circuits, feature dimensions have scaled deep into the nanometer regime.
Fundamental Principles of Nickel Silicide in Advanced Semiconductor Contact Engineering
In modern very large scale integration (VLSI) devices, establishing high-quality electrical contacts between active semiconductor regions and the metal routing network is a…
Fundamental Principles of Seed Layer Engineering in Advanced Semiconductor Manufacturing
In modern integrated circuit (IC) fabrication, particularly during front end of line processing and back-end metallization, achieving highly uniform and conformal thin films on…
Fundamentals of Stress Memorization Technique (SMT) in Advanced Silicon Manufacturing
SMT may retain part of a stress effect after a temporary film is removed. The available 40nm anneal precedes the cited cap, so the flow does not demonstrate the claimed sequence.
Mastering Void-Free Fill in Advanced Semiconductor Manufacturing: Physical Principles, Process Engineering, and Node Evolution
In modern ultra-large-scale integration (ULSI) complementary metal-oxide-semiconductor (CMOS) fabrication, the ability to seamlessly deposit materials into high-aspect-ratio…
Dual Gate Oxide Engineering: Physical Principles, Integration Challenges, and Node Evolution in Advanced CMOS Manufacturing
In modern microelectronics, the scaling of complementary metal-oxide-semiconductor (CMOS) technology has driven unprecedented integration density and processing performance.
Demystifying Contact Hole Etch: Process Physics, Integration Principles, and Advanced Node Challenges
The fabrication of modern integrated circuits is divided into distinct manufacturing phases, where the transition between the active device layer and the metal routing network…
Mastering the Dual Work Function Metal Gate: Principles, Integration, and Advanced Node Evolution
Why do nFET and pFET gates need different effective work functions? Trace the p-side metal, selective mask and n-side metal in a 7nm FinFET flow.
Wet Chemical Cleaning in BEOL: Principles and Mechanisms of EKC Post-Etch Residue Removal
In modern ultra-large-scale integration (ULSI) semiconductor manufacturing, defining features at advanced microelectronic scales requires precise execution across lithography…
First Via Level (V1): Linking Wiring Layers
The first via connects adjacent metal levels through dielectric. The 40nm flow verifies Via 1 patterning and etches, but the selected trail does not verify a specific fill metal.
Deep Dive into Local Via (V0) Integration: Principles, Physics, and Advanced Node Challenges
In modern integrated circuits, scaling transistor density requires severe reductions in device geometry and interconnect dimensions.