Stress memorization technique (SMT) uses a temporary stressed film and a thermal step to seek a retained device stress effect after film removal. The magnitude and sign of the effect depend on the stack, device orientation, geometry, and thermal sequence. The linked flows do not show a complete named SMT sequence.
Flow Context for Stress Memorization
The 7nm FinFET flow overview supplies transistor architecture context. In the free 40nm flow, the cited PolySi Anneal occurs before CESL deposition, so the two labels cannot be combined into an SMT cap–anneal–strip sequence. The cross-sections show neighboring film and thermal operations only.
The 40nm film and anneal panels are contextual and out of SMT sequence order.
Process map
7nm FinFET
Locate stress and nitride-related modules; the labels alone do not establish a full stress-memorization sequence.
Physics & Mechanism
Mechanical stress can alter semiconductor band structure and carrier transport, with the device response depending on stress direction and channel orientation . In a reported n-channel device experiment, a temporary tensile nitride cap was present through activation and removed afterward; a stress-related device effect remained. This one integration does not establish the effect for every transistor . The retained strain need not be permanent, localized only to a gate, or beneficial for every transistor. Direct device and stress measurements are needed to determine the outcome.
Process Principles
A claimed SMT sequence requires evidence for cap placement, anneal order, removal, and the measured response. Thermal processing must also be compatible with junctions and the surrounding stack. A stress film deposited after the relevant anneal cannot have caused that earlier anneal's memorization.
Challenges & Failure Modes
A weak or spatially variable retained effect, unwanted response in neighboring devices, film-removal damage, and interference with other thermal steps are possible. Their magnitude depends on the actual integration and cannot be read from an unrelated cross-section.
From Principle to Production Flow
An SMT implementation would be verified by its ordered film, thermal, and removal steps and by a device-level comparison. The 7nm flow overview gives context, not a verified SMT module. See capping layer and rapid thermal annealing for related mechanisms.
Technology Node Evolution
Stress engineering has been adapted to different transistor geometries. A technique that works for one planar or fin geometry does not automatically transfer its retained effect or integration sequence to another architecture.
Related Processes
SMT should be distinguished from a permanently retained stress liner and from pattern memorization, which concerns lithographic pattern transfer rather than retained device stress.
References
State of the Art and Future Perspectives in Advanced CMOS Technology
H. Radamson, Huilong Zhu, Zhenhua Wu, Xiaobin He, Hongxiao Lin, Jinbiao Liu et al. · Nanomaterials
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379