Understanding Thickness in Semiconductor Manufacturing: Physical Principles, Metrology, and Node Evolution

Introduction

In semiconductor manufacturing, "thickness" refers to the vertical dimension of a deposited or grown film layer—whether it is a gate dielectric, a metal interconnect, a spacer, or an epitaxial channel—measured perpendicular to the wafer surface [P2]. Although the concept sounds straightforward, the precision with which thickness must be controlled and measured in modern integrated circuit (IC) fabrication is extraordinary, often at the atomic or sub-nanometer scale [T1].

Thickness matters because nearly every electrical, optical, and mechanical property of a semiconductor device is a function of one or more layer thicknesses [P2]. The gate oxide thickness directly determines gate capacitance, drive current, threshold voltage roll-off, and tunneling leakage [T2]. The thickness of anti-reflective coating layers controls lithographic critical dimension uniformity by modulating reflectivity at the resist–substrate interface [P2]. Metal line thickness in single damascene integration governs interconnect resistance and electromigration lifetime [P2]. Even the thickness of a nucleation layer can determine whether a subsequent film grows amorphously or epitaxially [P2].

As the industry has progressed from planar MOSFETs at the 28 nm node to FinFETs at 14 nm and 7 nm, and now toward gate-all-around (GAA) nanoribbon transistors, the number of layers in a typical stack has multiplied and individual layer thicknesses have shrunk to a few atomic layers [A2]. This evolution has transformed thickness from a parameter that was "merely important" into one that is now a primary determinant of yield, performance, and reliability [P1].

Physics & Mechanism

Thickness as a Determinant of Device Physics

The fundamental reason thickness is so consequential lies in the physics of how carriers, fields, and waves interact with matter across a bounded dimension [T3]. Consider the gate dielectric in a MOSFET [T2]. The oxide capacitance per unit area is inversely proportional to oxide thickness: a thinner oxide increases the gate's electrostatic control over the channel, raising the drive current and suppressing short-channel effects such as threshold voltage roll-off [T2]. However, the same reduction in thickness intensifies the electric field across the dielectric and, below a certain thickness, enables quantum-mechanical tunneling, producing a gate leakage current that increases exponentially as the barrier becomes thinner [T2].

Similarly, in a strained heteroepitaxial layer, the film can be coherently strained to match the substrate lattice constant only up to a critical thickness, beyond which strain energy accumulates to the point where misfit dislocations nucleate and the film relaxes [T3]. The critical thickness depends on the lattice mismatch between the epitaxial layer and the substrate; a 2% mismatch typically yields a critical thickness on the order of 10 nm [T3]. This means that thickness is not merely a geometric specification—it is a thermodynamic boundary between a useful strained device and a defective one [A2].

Optical and Electromagnetic Interaction with Thickness

When light interacts with a thin film, interference occurs because waves reflected from the top and bottom surfaces of the film superpose [P2]. The phase difference between these reflections depends on the film's optical path length, which is the product of physical thickness and refractive index [P3]. For transparent films on a reflective substrate, constructive and destructive interference produces characteristic color changes that have historically been used as a visual thickness gauge for thermally grown silicon dioxide (SiO₂) [T1]. More precisely, spectroscopic reflectometry and ellipsometry exploit these interference patterns to extract thickness by solving an inverse problem based on Fresnel reflection coefficients and thin-film interference theory [P2].

In multilayer stacks—such as those found in 3D NAND flash memory with more than 200 layers—the interference pattern becomes highly complex because reflections from each interface contribute to the measured signal [P2]. The inverse problem of extracting individual layer thicknesses from a composite reflectance spectrum becomes ill-conditioned, meaning that small measurement noise can produce large errors in the inferred thickness values [P2].

Photoelectron Attenuation and Thickness

For ultrathin films (below approximately 10 nm), X-ray photoelectron spectroscopy (XPS) offers a powerful thickness measurement mechanism rooted in the photoelectric effect [P3]. When X-rays excite a sample, photoelectrons emitted from the substrate undergo inelastic scattering as they traverse an overlying film, causing exponential attenuation of the substrate signal with increasing film thickness [P3]. Simultaneously, photoelectrons originating from the film's own elements increase in intensity as the film thickens [P3]. The ratio of film-element to substrate-element peak intensities, combined with knowledge of the electron inelastic mean free path and atomic density, yields the film thickness [P3]. The limited escape depth of photoelectrons—a few nanometers in most solids—is precisely what makes XPS so sensitive to ultrathin film thickness [P3].

Process Principles

Deposition and Growth Parameters

The thickness of a film is determined by the cumulative effect of deposition or growth rate integrated over process time [P3]. In thermal oxidation of silicon, the growth kinetics transition from a linear regime (surface-reaction-limited) at short times to a parabolic regime (diffusion-limited) at longer times, following the Deal–Grove model [T1]. This means that the relationship between process time and resulting oxide thickness is nonlinear, and small temperature variations shift the reaction rate constants, producing thickness non-uniformity across the wafer [P2].

In chemical vapor deposition (CVD) and atomic layer deposition (ALD), the thickness is controlled by the number of deposition cycles (in ALD) or the product of precursor partial pressure, exposure time, and substrate temperature (in CVD) [P2]. ALD achieves self-limiting surface reactions, so thickness is determined by cycle count with sub-ångström precision, making it the preferred technique for ultrathin conformal films [P1]. In contrast, CVD thickness depends sensitively on local gas flow dynamics, temperature uniformity, and depletion effects, all of which can introduce within-wafer and wafer-to-wafer thickness variation [P2].

Directional Effects of Key Parameters

• Temperature: Increasing substrate temperature generally increases reaction rates in thermally activated processes, increasing deposition or growth rate and thus thickness for a fixed process time (Engineering Practice). In oxidation, higher temperature also shifts the linear-to-parabolic transition, altering the thickness–time relationship (Engineering Practice).
• Pressure: In plasma-enhanced processes, higher chamber pressure can increase radical density but reduce mean free path, affecting both deposition rate and conformality (Engineering Practice).
• Precursor flow: Increasing precursor flow rate tends to increase deposition rate up to a saturation point; beyond saturation, the rate plateaus and excess precursor may cause particle formation or thickness non-uniformity (Engineering Practice).
• Process time: For self-limiting processes (ALD), thickness increases linearly with cycle count [P2]. For non-self-limiting processes, thickness increases sub-linearly or linearly depending on the kinetic regime [P2].

Thickness Uniformity

Beyond the nominal thickness value, uniformity across the wafer is equally critical [P2]. Radial temperature gradients in a furnace or reactor produce systematic thickness gradients [P3]. Edge effects—where gas flow or plasma density differs near the wafer perimeter—can produce edge-to-center thickness variation [A2]. In batch processing, wafer-to-wafer spacing and boat position introduce additional variation sources (Engineering Practice). These non-uniformities translate directly into device parameter variation, which is why thickness uniformity is often specified as a primary process control metric alongside nominal thickness [P2].

Challenges & Failure Modes

Metrology Limitations

One of the most persistent challenges in thickness engineering is the difficulty of measuring thickness accurately at the nanoscale, especially for multilayer stacks [P2]. Physical measurement techniques such as stylus profilometry, scanning electron microscopy (SEM), and transmission electron microscopy (TEM) provide direct thickness information but require destructive sample preparation and are not suitable for in-line process control [T1]. Optical methods—spectrophotometry, spectroscopic ellipsometry—are non-destructive and fast but suffer from reduced accuracy as the number of layers increases, because the inverse problem becomes ill-conditioned [P2]. Ultrasonic methods lack sufficient spatial resolution for nanometer-scale films, and white-light interferometry has low phase sensitivity and material transparency constraints [P2].

For metal films, eddy-current sensing offers a non-contact, high-speed option [P1]. The technique exploits electromagnetic induction: an excitation coil induces eddy currents in the metal film, and the resulting opposing magnetic field alters the coil's impedance in a manner that reflects the film's thickness [P1]. However, traditional eddy-current measurements are highly sensitive to the distance (lift-off) between the sensor and the sample, which has historically limited its applicability in manufacturing environments [P1]. Recent advances using the slope of the lift-off curve (SLOC) in the impedance plane have shown promise in eliminating the lift-off effect, as this feature is approximately proportional to metal thickness and insensitive to distance perturbations [P1].

Thickness-Related Device Failures

When gate dielectric thickness is insufficient, quantum tunneling produces a gate leakage current that increases exponentially with decreasing thickness, leading to unacceptable static power consumption [T2]. Additionally, excessive electric fields across an ultra-thin dielectric can cause destructive breakdown, and long-term operation at high fields breaks weak chemical bonds at the silicon–oxide interface, generating oxide charge and threshold voltage shift [T2].

In epitaxial growth, exceeding the critical thickness for a given lattice mismatch causes the film to relax through misfit dislocation formation, degrading carrier mobility and device performance [T3]. In GAA nanoribbon transistors, non-uniform nanoribbon thickness across the stack can cause variations in drive current, electrostatic control, and source/drain epitaxial growth rates, ultimately degrading device performance uniformity [A2].

Package-Level Thickness Effects

At the package level, the thickness of individual components—die, die attach, solder, and molding compound—determines the position of the stress neutral plane [A1]. During solder reflow, coefficient of thermal expansion (CTE) mismatch among these layers produces bending and residual stress [A1]. If stress-sensitive circuitry is located far from the neutral plane, it experiences significant mechanical strain, causing electrical parameter drift [A1]. Introducing a stress-compensating chip of appropriate thickness above the main die can shift the neutral plane toward the sensitive circuits, reducing post-soldering stress shifts [A1].

Technology Node Evolution

28 nm and the Planar MOSFET Era

At the 28 nm node, planar MOSFETs remained the dominant transistor architecture [T2]. Gate oxide thickness had been scaled roughly in proportion to the gate length over many generations, from approximately 300 nm at the 10 µm technology node to only about 1.2 nm at the 65 nm node [T2]. By 28 nm, the gate dielectric was already approaching the tunneling limit, and high-k/metal gate (HKMG) technology was being adopted to increase physical thickness while maintaining or reducing equivalent oxide thickness (EOT) [T2]. This decoupling of physical thickness from electrical thickness was a pivotal innovation that allowed continued scaling without an explosion in gate leakage [T2]. The 28nm planar flow illustrates how these thickness-controlled steps were integrated [A2].

14 nm FinFET Transition

The transition to FinFET at 14 nm represented a paradigm shift in how thickness is used for electrostatic control [T2]. Instead of scaling the gate dielectric ever thinner, the 3D fin geometry provided superior gate control over the channel from three sides [A2]. However, this introduced new thickness-critical dimensions: the fin width, the fin height, and the thickness of conformal layers deposited on the fin sidewalls [P1]. The 14nm FinFET flow demonstrates the complexity of controlling these multiple thickness dimensions simultaneously [A2]. Conformal deposition processes such as ALD became essential because they could uniformly coat vertical fin sidewalls, ensuring that spacer and gate dielectric thicknesses were consistent on all surfaces [A2].

7 nm and Beyond

At 7 nm, the number of conformal layers multiplied, and the tolerance for thickness variation narrowed dramatically [P2]. The 7nm FinFET flow shows how epitaxial source/drain, spacer, and gate dielectric thicknesses must be controlled within a few atomic layers to maintain performance and yield [T2]. Techniques such as epitaxial growth with in-situ thickness monitoring became standard [P2].

Beyond 7 nm, the industry moved toward GAA nanoribbon transistors, where the channel itself is a suspended structure whose thickness directly determines the quantum confinement energy, the drive current, and the electrostatic integrity [A2]. Patented approaches now propose deliberately varying nanoribbon thickness within a single stack—making the bottom ribbon thicker to compensate for longer source-drain lengths—demonstrating that thickness has become a tunable design parameter rather than merely a process target [A2].

3D NAND and Multilayer Stacking

In parallel with logic scaling, 3D NAND flash has pushed multilayer stacking to over 200 layers, where each layer's thickness must be controlled and measured [P2]. The metrology challenge here is fundamentally different from logic: rather than measuring a single critical thickness, one must infer the thickness of each layer in a stack from a composite optical or electron signal [P2]. Machine-learning-based approaches have emerged as a complement to model-based inversion, learning the nonlinear mapping between spectral features and individual layer thicknesses from labeled training data [P2].

Related Processes

Thickness does not exist in isolation; it is tightly coupled to numerous adjacent process steps [P2]. In self-aligned double patterning, the thickness of the mandrel and spacer layers determines the final pitch and critical dimension of the patterned features [P2]. In critical dimension trim, the trim layer thickness controls how much material is removed, directly affecting the resulting line width [P2].

Surface preparation before deposition is equally important: surface cleaning removes native oxide and contaminants that would otherwise alter the initial growth regime, changing the thickness–time relationship in subsequent deposition [T1]. Similarly, the thickness of an anti-reflective coating must be precisely tuned to the exposure wavelength and the underlying film stack's optical properties to minimize reflectivity variation during lithography [P2].

In source drain recess, the recess depth—a thickness dimension in its own right—determines the volume available for epitaxial source/drain growth, which in turn affects strain transfer to the channel and thus carrier mobility [T1].

Future Outlook

The future of thickness engineering points toward several converging trends (Engineering Practice). First, as transistor channels move from fins to nanoribbons and ultimately to 2D materials, the concept of "thickness" is approaching the limit of a single atomic layer [P2]. XPS-based thickness measurement, already validated for 2D materials below 10 nm, will become increasingly important for characterizing monolayer and sub-monolayer films [P3].

Second, machine learning will play a growing role in multilayer thickness metrology, particularly for 3D NAND and other stacked architectures where model-based inversion is ill-conditioned [P2]. Data-driven approaches can achieve ångström-level accuracy when sufficient training data exists, though at the cost of physical interpretability [P2].

Third, in-package thickness engineering will grow in importance as heterogeneous integration and chiplet architectures become mainstream [A1]. The stress-compensating die concept [A1] illustrates how thickness can be used as a structural design variable to manage mechanical reliability, not just electrical performance.

Finally, the deliberate variation of thickness within a device—as exemplified by tuned nanoribbon stacks [A2]—signals a shift from uniform-thickness design rules to thickness-graded architectures, where each layer's thickness is individually optimized for its local function. This will demand unprecedented process control and metrology capabilities, pushing the boundaries of ALD, epitaxial growth, and in-line characterization technologies [P2].