Mastering Single Damascene: Process Physics, Integration Principles, and Advanced Node Evolution

Introduction

For decades, the continuous scaling of integrated circuits (ICs) has driven advances in computation speed, energy efficiency, and packing density. As active gate dimensions of metal-oxide-semiconductor field-effect transistors (MOSFETs) shrank, the dominant performance bottleneck shifted from intrinsic transistor switching delays to interconnect resistance-capacitance (RC) delays. In early generations of semiconductor manufacturing, interconnects were fabricated using a subtractive metallization scheme. In this approach, a blank metal film (typically aluminum) was deposited over the wafer, patterned using photolithography, and etched using reactive ion etching (RIE) to leave behind metal wires. The gaps between the wires were then filled with an inter-metal dielectric (IMD) such as undoped silicate glass.

However, as features scaled to the sub-micron regime, aluminum interconnects faced severe current density limitations due to electromigration and relatively high electrical resistivity. Copper emerged as an alternative material because of its lower electrical resistivity and superior electromigration resistance. Copper is difficult to etch, and in the damascene process when CMP is used, etching of the metal is not required [T1]. To bypass this chemical etching limitation, the industry adopted an inlaid metallization scheme known as the damascene process, which involves etching trenches or vias into a dielectric layer, filling those features with metal, and subsequently removing the excess metal to leave behind insulated conductive paths.

The two primary implementations of this inlay technique are single damascene and dual damascene. In a single damascene scheme, a single structural level is fabricated at a time; specifically, contacts or vias are formed, filled with metal, and polished flat before another dielectric layer is deposited and horizontal interconnect trenches are separately patterned, filled, and polished. A more advanced version of the damascene process provides both the via/contact and interconnect levels simultaneously [T1]. While dual damascene is widely utilized for upper-level metal routing due to fewer processing steps, single damascene remains essential for high-density contact levels (such as Middle-of-Line contact plugs) and the lowest metallization layers (M1, M2) where structural aspect ratios and tight overlay tolerances demand precise process control.

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Physics & Mechanism

The execution of a single damascene process sequence depends on synchronized chemical and physical surface interactions. The process flow consists of three main phases: anisotropic dielectric etching, bottom-up metallization, and chemical mechanical planarization (CMP).

1. Anisotropic Dielectric Etching

The first phase of single damascene transfers the lithographic pattern into the underlying interlayer dielectric (ILD) or IMD layer. This is achieved through plasma etching, coupling physical sputtering with chemical reactions to achieve high anisotropy and material selectivity.

The plasma environment consists of a low-pressure discharge containing electrons, ions, neutral radicals, and excited species:

• Electron-Impact Ionization: High-frequency electric fields accelerate free electrons, which collide with feed gases (such as fluorocarbons) to generate reactive radicals and positive ions.
• Sheath Field Acceleration: An electric field established adjacent to the wafer surface accelerates positive ions vertically toward the substrate, providing directional kinetic energy.
• Ion-Radical Synergism: Neutral radicals adsorb onto the dielectric surface. Under vertical ion bombardment, energy transferred from incoming ions breaks local surface bonds and lowers activation energy. Fluorine-containing species react with silicon dioxide or low-k dielectric matrices to form volatile reaction products that are removed by the vacuum system.
• Sidewall Passivation: To prevent isotropic lateral etching from radical attack, fluorocarbon precursors continuously deposit a thin polymeric passivation layer on trench sidewalls. Vertical ion flux sputters away the polymer at the bottom of the feature while leaving sidewall passivation intact, ensuring directional profile control.

2. Barrier, Liner, and Metal Deposition Mechanisms

Once dielectric trenches or vias are etched, direct copper deposition onto dielectric materials would lead to thermal and electrical instability, as copper readily diffuses into dielectrics. To prevent diffusion and promote adhesion, a thin, conformal barrier layer (such as tantalum, tantalum nitride, titanium, or titanium nitride) is deposited along feature sidewalls and bottoms, followed by a thin conductive liner layer (such as cobalt or ruthenium).

Following barrier and liner deposition, a conductive seed layer is deposited to provide an electrical path for electroplating. Bulk metal fill is performed using electrochemical deposition (ECD). To achieve a void-free fill in narrow features, organic bath additives (suppressors, accelerators, and levelers) regulate growth kinetics. Suppressor molecules slow deposition at the top corners and upper sidewalls, while accelerator molecules accumulate at the narrow bottom of the feature, driving bottom-up superfilling and preventing keyhole voids.

3. Surface Planarization via CMP

The metal electroplating step leaves excess overburden metal across the wafer surface. Excess metal, along with the underlying barrier and liner layers on the dielectric field, must be removed to isolate individual lines. This is accomplished using chemical mechanical planarization (CMP).

CMP relies on a combination of chemical oxidation and mechanical abrasion. A chemical slurry containing oxidizers and complexing agents reacts with the metal surface to form a soft passivated surface layer. Abrasive nanoparticles suspended in the slurry, driven by a rotating polishing pad under applied pressure, shear away this surface layer. Higher effective pressure at surface high points accelerates local removal rates, resulting in global planarization.

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Process Principles

Optimizing single damascene integration requires managing parameter interactions across lithography, etch, deposition, and planarization modules.

Lithography and Etch Interactions

Trench and via patterns are established using photolithography over a bottom anti-reflective coating (BARC). The BARC layer suppresses reflection from underlying reflective layers, controlling standing wave effects and feature distortion.

During dry etching, fluorocarbon plasma chemistry controls the balance between etching and polymer passivation:

• Increasing the F:C Ratio: Adding oxygen or using fluorine-rich precursors shifts equilibrium toward chemical etching, increasing etch rates but potentially reducing mask selectivity and causing feature bowing.
• Decreasing the F:C Ratio: Using polymerizing precursors increases sidewall polymer protection, improving anisotropy, though excessive passivation can induce etch stop or excessive profile taper.
• RF Bias Power: Increasing bias power accelerates ion bombardment, enhancing physical sputtering at the trench bottom for high-aspect-ratio features, though excessive ion energy can cause physical damage to porous low-k dielectrics.

Metallization Parameter Interactions

Electrochemical deposition efficiency depends on feature aspect ratio (depth-to-width ratio). As trench widths decrease, fluid diffusion into features becomes restricted:

• Additive Balance: Adjusting the ratio of suppressors to accelerators prevents premature pinch-off at upper feature corners.
• Current Profiling: Applying low initial current density encourages uniform initial nucleation before ramping current density to fill bulk overburden, balancing defect control with throughput.

CMP Parameter Interactions

In chemical mechanical planarization, local polish rates depend on applied downforce, relative pad velocity, and chemical activity. High downforce increases removal rates but increases pad deflection into wide features, worsening dishing. Planarization process evaluations demonstrate a degradation of Cu to liner selectivity with decrease in Cu interconnect line width [P1].

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Challenges & Failure Modes

1. Dishing and Erosion

During CMP, differences in mechanical hardness and chemical removal rates between metal and dielectric lead to surface non-planarity:

• Dishing: Occurs when the polishing pad deflects into wide metal lines, selectively removing metal below the surrounding dielectric plane.
• Erosion: Occurs in dense arrays of narrow lines where thin dielectric field regions are removed faster than isolated field regions under local pad loading.

Both dishing and erosion reduce the conductive cross-sectional area, increasing line resistance and signal degradation.

2. Electromigration

High current densities in fine metal lines drive momentum transfer from conduction electrons to metal atoms, causing directional atomic migration. Over time, this transport creates voids near the cathode end (leading to open circuits) and extrusions near the anode end (causing short circuits to neighboring lines). In copper interconnects, the upper interface between copper and the overlying dielectric capping layer represents a primary pathway for diffusion.

3. Dielectric Degradation and Plasma Damage

Porous low-k dielectrics used to minimize inter-line capacitance are susceptible to plasma-induced damage during etch and strip steps. Plasma radicals can strip hydrophobic carbon groups from the dielectric matrix, leaving hydrophilic species that absorb ambient moisture, which increases the effective dielectric constant and elevates line-to-line leakage current.

4. Overlay and Alignment Margins

As contact and via dimensions shrink, overlay error between lithography steps reduces effective contact area, increasing interfacial resistance. Severe misalignment can cause etching steps to encroach into adjacent isolation regions, causing unwanted electrical shorts.

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Technology Node Evolution

1. Mature Planar Nodes

In mature planar CMOS architectures, single damascene was widely implemented at the contact level using tungsten plugs, while copper single damascene was applied at the lowest metallization layer (M1) to manage tight pitches and overlay constraints. Upper routing layers transitioned to dual damascene to minimize thermal budget and mask count.

2. FinFET Nodes

With 3D FinFET architectures, increased contact aspect ratios and tighter pitch constraints made traditional tungsten contact plugs prone to voiding. Cobalt single damascene was introduced for local contacts (M0/M1) to reduce contact resistance at nickel silicide or cobalt silicide interfaces and improve electromigration resistance under high current densities.

3. Nanosheet and Advanced Nodes

At sub-7nm nodes, electron scattering at grain boundaries and thin barrier interfaces sharply increases copper line resistivity. Alternative metals such as cobalt and ruthenium, which exhibit shorter electron mean free paths and do not require thick diffusion barriers, are integrated using single damascene schemes for local metallization levels.

In backside power delivery networks (BSPDNs), single damascene is utilized to form multi-stage vertical contacts linking backside power lines to active devices, providing precise profile control and alignment margin management across disparate material interfaces.

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Related Processes

• Wet Chemical Cleaning: Prior to barrier deposition, exposed contacts and trenches are cleaned using formulations such as dilute hydrofluoric acid (DHF) to remove native oxides and residues while protecting sensitive dielectrics.
• Silicide Contacts: Single damascene contact plugs interface directly with FEOL salicide layers on source, drain, and gate structures.
• Dielectric Capping: Following CMP planarization, a dielectric capping layer is deposited over polished lines to seal the metal and mitigate interfacial electromigration.

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Future Outlook

For future sub-2nm nodes, single damascene integration continues to evolve alongside advanced material synthesis and precision etching techniques. Area-selective deposition (ASD) enables self-aligned material growth on dielectric surfaces while inhibiting deposition on adjacent features, relaxing overlay constraints. Simultaneously, atomic layer etching (ALE) provides angstrom-scale removal control, producing smooth sidewall profiles that minimize electron scattering in sub-10nm conductive lines.